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authorUwe Hermann <uwe@hermann-uwe.de>2010-12-08 08:22:04 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-08 08:22:04 +0000
commitd35192544675575276482e5ce65d1b6a6fd9e4a0 (patch)
tree6bf1a6e9cd6989ddf2e70ffa8cde40b8239369c4 /src/mainboard/jetway
parent8301d8348a0848d56fdf4dbd76acd6bdcd3fc944 (diff)
downloadcoreboot-d35192544675575276482e5ce65d1b6a6fd9e4a0.tar.xz
Move "select CACHE_AS_RAM" lines from boards into CPU socket.
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM" into the socket directories, and remove it from the individual boards. Do the same for Intel CPUs/sockets where all boards use CAR. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/pa78vm5/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig
index d9bf9448ad..0f35db224b 100644
--- a/src/mainboard/jetway/pa78vm5/Kconfig
+++ b/src/mainboard/jetway/pa78vm5/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_MAINBOARD_RESOURCES
- select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID