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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 07:55:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-18 20:01:48 +0200 |
| commit | 5276941c8b9a3294fda4eb5d102c8333688d29a5 (patch) | |
| tree | 27739465f0d6bb065f331e40cc468b8fad885461 /src/mainboard/jetway | |
| parent | e93e7102cf63a122d2f69a24678f8bec38af88a6 (diff) | |
| download | coreboot-5276941c8b9a3294fda4eb5d102c8333688d29a5.tar.xz | |
AMD boards: Fix romstage main() declaration
Boards incorrectly used intel include file for AMD board.
Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/j7f2/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 42aaa0c05c..0de239c6fa 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> +#include <cpu/amd/car.h> #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> @@ -80,7 +81,6 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include <cpu/intel/romstage.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ |