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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-05-06 23:53:09 +1000 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-13 10:03:38 +0200 |
| commit | e61dd0f7a2be83ce5ba87d74f7384111576ffd49 (patch) | |
| tree | a9f2c51500bbd8702cf039c8e620653d25c4b4d8 /src/mainboard/jetway | |
| parent | 216a619a74d61f66e3d3e1d668028d11a8868b4d (diff) | |
| download | coreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.tar.xz | |
southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/romstage.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 8c05236515..bfd24cb60c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -44,10 +44,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -/* FIXME: should not include .c files */ -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) @@ -188,14 +184,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif /* CONFIG_HAVE_ACPI_RESUME */ - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); |