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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-10-05 13:40:31 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-10-05 13:40:31 +0000
commit5692c5733633bfb8b23f1111de152eff0233b713 (patch)
treed315817986c71d6710f75dceb87689b95e1bff53 /src/mainboard/jetway
parentd0835953506263b0d9218b62176693315f2ef2f3 (diff)
downloadcoreboot-5692c5733633bfb8b23f1111de152eff0233b713.tar.xz
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index fc18ba9887..0ccfaccb5c 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -66,10 +66,7 @@ static int smbus_read_byte(u32 device, u32 address);
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
-#if CONFIG_USBDEBUG
-#include "southbridge/amd/sb700/sb700_enable_usbdebug.c"
-#include "pc80/usbdebug_serial.c"
-#endif
+#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>