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authorMike Banon <mikebdp2@gmail.com>2020-02-13 16:16:01 +0000
committerPatrick Georgi <pgeorgi@google.com>2020-02-24 13:54:59 +0000
commitc896df7f158cf759906f4f164330fb552bbe0fec (patch)
tree63ec22c010467c201412df71447e1c7219668551 /src/mainboard/jetway
parente3229a5192a84c04a4d1f0307d8cfb5e864b7ff3 (diff)
downloadcoreboot-c896df7f158cf759906f4f164330fb552bbe0fec.tar.xz
mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/Kconfig4
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/Kconfig.name4
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/Makefile.inc2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/bootblock.c (renamed from src/mainboard/jetway/nf81-t56n-lf/romstage.c)6
4 files changed, 6 insertions, 10 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
index dfa01b93a6..d2dda6725f 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig
@@ -14,14 +14,10 @@
# GNU General Public License for more details.
#
-config BOARD_JETWAY_NF81_T56N_LF
- def_bool n
-
if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS
def_bool y
- #select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
index 0b676274ae..2e660f937c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
+++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_JETWAY_NF81_T56N_LF
-# bool"NF81_T56N_LF"
+config BOARD_JETWAY_NF81_T56N_LF
+ bool "NF81_T56N_LF"
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
index ba56286636..bf86007cec 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
+++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
@@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI
pci$(stripped_ahcibios_id).rom-type := optionrom
endif
+bootblock-y += bootblock.c
+
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c
index 5e61bddfcc..5ecfaf74f8 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c
@@ -14,16 +14,14 @@
* GNU General Public License for more details.
*/
-#include <northbridge/amd/agesa/state_machine.h>
+#include <bootblock_common.h>
#include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h>
-#include <sb_cimx.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
-void board_BeforeAgesa(struct sysinfo *cb)
+void bootblock_mainboard_early_init(void)
{
- sb_Poweron_Init();
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}