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authorJitao Shi <jitao.shi@mediatek.com>2020-01-14 21:23:44 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 15:38:39 +0000
commitf68cc8151310bf4477bf48ebd95b5473dab8ebde (patch)
treea68ceeca1e643d4bf07c83e923bc00e9591d8fee /src/mainboard/jetway
parent443fbd70495404a99a17be990518c237f3654227 (diff)
downloadcoreboot-f68cc8151310bf4477bf48ebd95b5473dab8ebde.tar.xz
soc/mediatek: dsi: reduce the hbp and hfp for phy timing
The extra data transfer in DSI, namely, lpx, hs_prepare, hs_zero, hs_exit and the sof/eof of DSI packets, will enlarge the line time, which causes the real frame on dsi bus to be lower than the one calculated by video timing. Therefore, hfp_byte is reduced by d_phy to compensate the increase in time by the extra data transfer. However, if hfp_byte is not large enough, the hsync period will be increased on DSI data, leading to display scrolling in firmware screen. To avoid this situation, this patch changes the DSI Tx driver to reduce both hfp_byte and hbp_byte, with the amount proportional to hfp and hbp, respectively. Refer to kernel's change in CL:1915442. Also rename 'phy_timing' to 'timing' to sync with kernel upstream. Since the phy timing initialization sequence has been corrected, the m value adjustment in the analogix driver can be removed. BUG=b:144824303 BRANCH=kukui TEST=emerge-jacuzzi coreboot TEST=Boots and sees firmware screen on krane and juniper TEST=No scrolling issue on juniper AUO and InnoLux panels Change-Id: I10a4d8a4fb41c309fa1917cf1cdf19dabed98227 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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