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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-07 12:19:10 +0200
committerMartin Roth <martinroth@google.com>2018-08-09 15:56:32 +0000
commit08fc8fff255c3aa27362655887a5f5bcd786857c (patch)
tree3947fb4c6ac77a6e357cd8968f7159d0c5888a47 /src/mainboard/jetway
parent2f79eb3fd567b7578378c4acbecaf2502d1982f4 (diff)
downloadcoreboot-08fc8fff255c3aa27362655887a5f5bcd786857c.tar.xz
src/mainboard: Fix typo
Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/mainboard.c2
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/mptable.c2
-rw-r--r--src/mainboard/jetway/pa78vm5/resourcemap.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index 205b6559cb..567a58666d 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -87,7 +87,7 @@ static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
*/
/*
* Persimmon has PCI slot INTA/B/C/D connected to PIRQE/F/G/H
- * but because PCI INT_PIN swizzling isnt implemented to match
+ * but because PCI INT_PIN swizzling isn't implemented to match
* the IDSEL (dev 3) of the slot, the table is adjusted for the
* swizzle and INTA is connected to PIRQH so PINA/B/C/D on
* off-chip devices should get mapped to PIRQH/E/F/G.
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index 92564c264a..a933f60d80 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
- /* Intialize the MP_Table */
+ /* Initialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c
index d6c860892b..58b681f197 100644
--- a/src/mainboard/jetway/pa78vm5/resourcemap.c
+++ b/src/mainboard/jetway/pa78vm5/resourcemap.c
@@ -122,7 +122,7 @@ static void setup_mb_resource_map(void)
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
+ * This field defines the upp address bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,