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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-25 21:23:37 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-28 21:50:12 +0000
commit5b672d595411a50012d3d232db6d886818d44893 (patch)
tree06ead78b90df1ec04fe71c29f52068290821f115 /src/mainboard/jetway
parentb0ae42b5bb7fe7c9f6e8301bff8fbabe95294c62 (diff)
downloadcoreboot-5b672d595411a50012d3d232db6d886818d44893.tar.xz
soc/amd/common: Access ACPIMMIO via proper symbols
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 2129509d55..64ba978ec2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -48,7 +48,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = ACPIMMIO_GPIO_BASE_100;
+ GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
switch (ResetInfo->ResetId)
{
case 46: /* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */