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authorAngel Pons <th3fanbus@gmail.com>2020-05-21 01:06:28 +0200
committerNico Huber <nico.h@gmx.de>2020-05-26 11:46:09 +0000
commit5f82370d7bc4ba385ae8911cbfdabd4450f0e944 (patch)
tree6ffa0f261795f32ddffa7b03036f0774df0cd3d0 /src/mainboard/jetway
parent41b820cbd66da001b02a426a7b5cf1b7f011702a (diff)
downloadcoreboot-5f82370d7bc4ba385ae8911cbfdabd4450f0e944.tar.xz
AGESA f14/f15tn/f16kb: Factor out PCI MMIO base/size
We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values everywhere, so we might as well factor them out. As we have equivalent Kconfig options in coreboot, also deprecate overriding them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/buildOpts.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index 02a416a8c1..a20d133f3a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -68,9 +68,6 @@
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
-#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
-#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
-
#define BLDCFG_VRM_CURRENT_LIMIT 24000
//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000