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authorPatrick Georgi <patrick@georgi-clan.de>2010-11-20 10:31:00 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-11-20 10:31:00 +0000
commit9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (patch)
tree325b7b6abc1d4514d52ad1f726d9be4fa00d0454 /src/mainboard/jetway
parent622824cadbbbe003bc3e8c97694d2cf6bae0de9b (diff)
downloadcoreboot-9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a.tar.xz
Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/pa78vm5/romstage.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 35cf843692..6944fcc302 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -92,17 +92,11 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
-
-
+#include <spd.h>
#define RC00 0
#define RC01 1
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{