mainboard/jetway/nf81-t56n-lf: Documentation cosmetics

Keep under 80 colums and Doxygen'ify inline documentation somewhat.
Strip some whitespace bulk while here and refactor a little as to line
wrap.

Additionally, following the reasoning of:
0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
remove some fluff from buildOpts.c

Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5481
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

14 files changed, 282 insertions, 358 deletions

diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 0502e5a573..441661e6ff 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -401,13 +401,13 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr)
 	ResetType = Data;
 	StdHeader = ConfigPtr;
 
-	//
-	// Perform the RESET based upon the ResetType. In case of
-	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
-	// AmdResetManager. During the critical condition, where reset is required
-	// immediately, the reset will be invoked directly by writing 0x04 to port
-	// 0xCF9 (Reset Port).
-	//
+	/*
+	 * Perform the RESET based upon the ResetType. In case of
+	 * WARM_RESET_WHENEVER and COLD_RESET_WHENEVER, the request will go to
+	 * AmdResetManager. During the critical condition, where reset is required
+	 * immediately, the reset will be invoked directly by writing 0x04 to port
+	 * 0xCF9 (Reset Port).
+	 */
 	switch (ResetType) {
 	case WARM_RESET_WHENEVER:
 	case COLD_RESET_WHENEVER:
@@ -453,8 +453,9 @@ AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *Conf
 /* Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr)
 {
-	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
-	// Make sure the right speed settings are selected.
+	/* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
+	 * Make sure the right speed settings are selected.
+	 */
 	((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
 	return AGESA_SUCCESS;
 }
@@ -470,6 +471,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *
 {
 	return AGESA_SUCCESS;
 }
+
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr)
 {
@@ -484,7 +486,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr
 
 	FcnData = Data;
 	ResetInfo = ConfigPtr;
-	// Get SB800 MMIO Base (AcpiMmioAddr)
+	/* Get SB800 MMIO Base (AcpiMmioAddr) */
 	WriteIo8(0xCD6, 0x27);
 	Data8 = ReadIo8(0xCD7);
 	Data16=Data8<<8;
@@ -496,7 +498,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr
 	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 	switch (ResetInfo->ResetId)
 	{
-	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
+	case 46:	/* GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot */
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
 			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
index 1d63f9b926..2c509a24ab 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
@@ -40,13 +40,12 @@ typedef struct _BIOS_BUFFER_NODE {
 	uint32_t BufferSize;
 	uint32_t NextNodeOffset;
 } BIOS_BUFFER_NODE;
-/*
- * CALLOUTS
- */
+
+/* Callouts */
 AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr);
 
-/* REQUIRED CALLOUTS
- * AGESA ADVANCED CALLOUTS - CPU
+/* Required Callouts
+ * AGESA Advanced Callouts - CPU
  */
 AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr);
 AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr);
@@ -56,7 +55,7 @@ AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr);
 AGESA_STATUS BiosGetIdsInitData (uint32_t Func, uint32_t Data, void *ConfigPtr);
 
 /* AGESA Advanced Callouts - Memory */
-AGESA_STATUS BiosReadSpd (uint32_t Func,uint32_t	Data,void *ConfigPtr);
+AGESA_STATUS BiosReadSpd (uint32_t Func, uint32_t Data, void *ConfigPtr);
 
 /* BIOS default RET */
 AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr);
@@ -72,4 +71,4 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr);
 
-#endif //_BIOS_CALLOUT_H_
+#endif /* _BIOS_CALLOUT_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
index e1f18a9836..0630008f6e 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
+++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
@@ -33,5 +33,3 @@ ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
-
-
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
index 3cc9c898cf..347a7b76d5 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
@@ -26,7 +26,6 @@
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
-/*---------------------------------------------------------------------------------------*/
 /**
  *	OemCustomizeInitEarly
  *
@@ -48,52 +47,95 @@ void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly)
 
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
+/**
+ * @brief Initialize Port descriptors
+ */
 PCIe_PORT_DESCRIPTOR PortList [] = {
-		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+		/* (PCIe port, Lanes 4, PCI Device Number 4, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT,
+							GNB_GPP_PORT4_CHANNEL_TYPE,
+							4,
+							GNB_GPP_PORT4_HOTPLUG_SUPPORT,
+							GNB_GPP_PORT4_SPEED_MODE,
+							GNB_GPP_PORT4_SPEED_MODE,
+							GNB_GPP_PORT4_LINK_ASPM,
+							46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+		/* (PCIe port, Lanes 5, PCI Device Number 5, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT,
+							GNB_GPP_PORT5_CHANNEL_TYPE,
+							5,
+							GNB_GPP_PORT5_HOTPLUG_SUPPORT,
+							GNB_GPP_PORT5_SPEED_MODE,
+							GNB_GPP_PORT5_SPEED_MODE,
+							GNB_GPP_PORT5_LINK_ASPM,
+							46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+		/* (PCIe port, Lanes 6, PCI Device Number 6, ...) */
 		{
-			0, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT,
+							GNB_GPP_PORT6_CHANNEL_TYPE,
+							6,
+							GNB_GPP_PORT6_HOTPLUG_SUPPORT,
+							GNB_GPP_PORT6_SPEED_MODE,
+							GNB_GPP_PORT6_SPEED_MODE,
+							GNB_GPP_PORT6_LINK_ASPM,
+							46)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+		/* (PCIe port, Lanes 7, PCI Device Number 7, ...) */
 		{
 			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT,
+							GNB_GPP_PORT7_CHANNEL_TYPE,
+							7,
+							GNB_GPP_PORT7_HOTPLUG_SUPPORT,
+							GNB_GPP_PORT7_SPEED_MODE,
+							GNB_GPP_PORT7_SPEED_MODE,
+							GNB_GPP_PORT7_LINK_ASPM,
+							0)
 		},
-		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+		/* (PCIe port, Lanes 8, PCI Device Number 8, ...) */
 		{
-			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			/* Descriptor flags. IMPORTANT! Terminate last element of array */
+			DESCRIPTOR_TERMINATE_LIST,
 			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT,
+							GNB_GPP_PORT8_CHANNEL_TYPE,
+							8,
+							GNB_GPP_PORT8_HOTPLUG_SUPPORT,
+							GNB_GPP_PORT8_SPEED_MODE,
+							GNB_GPP_PORT8_SPEED_MODE,
+							GNB_GPP_PORT8_LINK_ASPM,
+							0)
 		}
 };
 
+/**
+ * @brief Initialize Ddi descriptors
+ */
 PCIe_DDI_DESCRIPTOR DdiList [] = {
-		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+		/* (DDI interface Lanes 8:11, DdA, ...) */
 		{
-			0,	 //Descriptor flags
+			0,
 			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */
 			{ConnectorTypeLvds, Aux1, Hdp1}
 		},
-		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+		/* (DDI interface Lanes 12:15, DdB, ...) */
 		{
-			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags	!!!IMPORTANT!!! Terminate last element of array
+			/* Descriptor flags. IMPORTANT! Terminate last element of array */
+			DESCRIPTOR_TERMINATE_LIST,
 			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-			//PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
+			/* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */
 			{ConnectorTypeDP, Aux2, Hdp2}
 		}
 };
@@ -105,38 +147,46 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
 		&DdiList[0]
 };
 
-	// GNB PCIe topology Porting
-
-	//
-	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	//
-	AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
+	/**
+	 * @brief GNB PCIe topology Porting
+	 *
+	 * Allocate buffer for
+	 * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	 */
+	AllocHeapParams.RequestedBufferSize =
+		sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
 
 	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-	if ( Status!= AGESA_SUCCESS) {
-	// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-	ASSERT(FALSE);
-	return;
+
+	/**
+	 * Could not allocate buffer for
+	 * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	 */
+	if (Status!= AGESA_SUCCESS) {
+		ASSERT(FALSE);
+		return;
 	}
 
-	BrazosPcieComplexListPtr	=	(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	BrazosPcieComplexListPtr =
+		(PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
 	AllocHeapParams.BufferPtr += sizeof(Brazos);
-	BrazosPciePortPtr		 =	(PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+	BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
 	AllocHeapParams.BufferPtr += sizeof(PortList);
-	BrazosPcieDdiPtr			=	(PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+	BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 
 	memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
 	memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
 	memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
 
-
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =	(PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList	=	(PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList =
+		(PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList =
+		(PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr;
 
 	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-	InitEarly->GnbConfig.PsppPolicy		= 0;
+	InitEarly->GnbConfig.PsppPolicy = 0;
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index 20877f10e2..dd6f7d7c7d 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,46 +24,61 @@
 #include <vendorcode/amd/agesa/f14/AGESA.h>
 #include <vendorcode/amd/agesa/f14/Lib/amdlib.h>
 
-//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT4_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT4_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT4_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/**
+ * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
+ *
+ * GNB_GPP_PORT?_PORT_PRESENT
+ *  0:Disable 1:Enable
+ *
+ * GNB_GPP_PORT?_SPEED_MODE
+ *  0:Auto 1:GEN1 2:GEN2
+ *
+ * GNB_GPP_PORT?_LINK_ASPM
+ *  0:Disable 1:L0s 2:L1 3:L0s+L1
+ *
+ * GNB_GPP_PORT?_CHANNEL_TYPE -
+ *  0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ *  3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+ *
+ * GNB_GPP_PORT?_HOTPLUG_SUPPORT
+ *  0:Disable 1:Basic 3:Enhanced
+ */
+
+/* GNB GPP 4 */
+#define GNB_GPP_PORT4_PORT_PRESENT		1
+#define GNB_GPP_PORT4_SPEED_MODE		2
+#define GNB_GPP_PORT4_LINK_ASPM			3
+#define GNB_GPP_PORT4_CHANNEL_TYPE		4
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT5_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT5_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT5_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 5 */
+#define GNB_GPP_PORT5_PORT_PRESENT		1
+#define GNB_GPP_PORT5_SPEED_MODE		2
+#define GNB_GPP_PORT5_LINK_ASPM			3
+#define GNB_GPP_PORT5_CHANNEL_TYPE		4
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT6_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT6_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT6_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 6 */
+#define GNB_GPP_PORT6_PORT_PRESENT		1
+#define GNB_GPP_PORT6_SPEED_MODE		2
+#define GNB_GPP_PORT6_LINK_ASPM			3
+#define GNB_GPP_PORT6_CHANNEL_TYPE		4
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT		0	//0:Disable 1:Enable
-#define GNB_GPP_PORT7_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT7_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT7_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 7 */
+#define GNB_GPP_PORT7_PORT_PRESENT		0
+#define GNB_GPP_PORT7_SPEED_MODE		2
+#define GNB_GPP_PORT7_LINK_ASPM			3
+#define GNB_GPP_PORT7_CHANNEL_TYPE		4
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT	0
 
-//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT		1	//0:Disable 1:Enable
-#define GNB_GPP_PORT8_SPEED_MODE		2	//0:Auto 1:GEN1 2:GEN2
-#define GNB_GPP_PORT8_LINK_ASPM			3	//0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE		4	//0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-											 //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
-#define GNB_GPP_PORT8_HOTPLUG_SUPPORT	0	//0:Disable 1:Basic 3:Enhanced
+/* GNB GPP 8 */
+#define GNB_GPP_PORT8_PORT_PRESENT		1
+#define GNB_GPP_PORT8_SPEED_MODE		2
+#define GNB_GPP_PORT8_LINK_ASPM			3
+#define GNB_GPP_PORT8_CHANNEL_TYPE		4
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT	0
 
 void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);
 
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
index 2096ab3226..b513fcec18 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
@@ -44,6 +44,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_ta
 	lens += acpigen_write_name_dword("TOM1", msr.lo);
 	msr = rdmsr(TOP_MEM2);
 	/*
+	 * FIXME: remove this work-around and url.. WinXP is EOL'ed any way.
 	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
 	 * here.
 	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
@@ -108,7 +109,7 @@ unsigned long acpi_fill_hest(acpi_hest_t *hest)
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-	// Not implemented
+	/* Not implemented */
 	return current;
 }
 
@@ -164,7 +165,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	memcpy(dsdt, &AmlCode, dsdt->length);
 	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
-	/* FACS */ // it needs 64 bit alignment
+	/* FACS - it needs 64 bit alignment */
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
 	facs = (acpi_facs_t *) current;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
index c9824f1de3..4f25756af7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
@@ -17,11 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/*-----------------------------------------------------------------------------
- *						M O D U L E S		U S E D
- *-----------------------------------------------------------------------------
- */
-
 #include "agesawrapper.h"
 #include "BiosCallOuts.h"
 #include "PlatformGnbPcieComplex.h"
@@ -41,11 +36,6 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*------------------------------------------------------------------------------
- *					D E F I N I T I O N S		A N D		M A C R O S
- *------------------------------------------------------------------------------
- */
-
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
@@ -58,25 +48,6 @@ void *AcpiWheaMce	= NULL;
 void *AcpiWheaCmc	= NULL;
 void *AcpiAlib		= NULL;
 
-/*------------------------------------------------------------------------------
- *				T Y P E D E F S		 A N D		 S T R U C T U R E S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *						E X P O R T E D		F U N C T I O N S
- *------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------
- *						L O C A L		F U N C T I O N S
- *------------------------------------------------------------------------------
- */
 AGESA_STATUS agesawrapper_amdinitcpuio(void)
 {
 	pci_devfn_t dev;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
index bad9b8083d..b97b6d5aef 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
@@ -17,11 +17,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *						 M O D U L E S		U S E D
- *----------------------------------------------------------------------------------------
- */
-
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -29,49 +24,28 @@
 #include <vendorcode/amd/agesa/f14/AGESA.h>
 
 
-/*----------------------------------------------------------------------------------------
- *					 D E F I N I T I O N S		A N D		M A C R O S
- *----------------------------------------------------------------------------------------
+/**
+ * Define AMD Ontario APU SSID/SVID
  */
-/* Define AMD Ontario APPU SSID/SVID */
 #define AMD_APU_SVID		0x1022
 #define AMD_APU_SSID		0x1234
 #define PCIE_BASE_ADDRESS	 CONFIG_MMCONF_BASE_ADDRESS
 
 enum {
-	PICK_DMI,		/* DMI Interface */
-	PICK_PSTATE,	/* Acpi Pstate SSDT Table */
-	PICK_SRAT,		/* SRAT Table */
-	PICK_SLIT,		/* SLIT Table */
-	PICK_WHEA_MCE,	/* WHEA MCE table */
-	PICK_WHEA_CMC,	/* WHEA CMV table */
-	PICK_ALIB,		/* SACPI SSDT table with ALIB implementation */
+	PICK_DMI,		/**< DMI Interface */
+	PICK_PSTATE,	/**< Acpi Pstate SSDT Table */
+	PICK_SRAT,		/**< SRAT Table */
+	PICK_SLIT,		/**< SLIT Table */
+	PICK_WHEA_MCE,	/**< WHEA MCE table */
+	PICK_WHEA_CMC,	/**< WHEA CMV table */
+	PICK_ALIB,		/**< SACPI SSDT table with ALIB implementation */
 };
 
-/*----------------------------------------------------------------------------------------
- *					T Y P E D E F S		 A N D		 S T R U C T U	R E S
- *----------------------------------------------------------------------------------------
- */
-
 typedef struct {
 	uint32_t CalloutName;
 	AGESA_STATUS (*CalloutPtr) (uint32_t Func, uint32_t Data, void* ConfigPtr);
 } BIOS_CALLOUT_STRUCT;
 
-/*----------------------------------------------------------------------------------------
- *		P R O T O T Y P E S		 O F		 L O C A L		 F U	N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- *						E X P O R T E D		F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- *						L O C A L		F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
 
 AGESA_STATUS agesawrapper_amdinitreset(void);
 AGESA_STATUS agesawrapper_amdinitearly(void);
@@ -92,4 +66,4 @@ void * agesawrapper_getlateinitptr(int);
 
 uint32_t GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
 
-#endif
+#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
index aa985a52e1..7cf274e597 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c
@@ -50,14 +50,13 @@
 
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
-
-/*	Select the cpu family.	*/
+/* Select the cpu family. */
 #define INSTALL_FAMILY_10_SUPPORT FALSE
 #define INSTALL_FAMILY_12_SUPPORT FALSE
 #define INSTALL_FAMILY_14_SUPPORT TRUE
 #define INSTALL_FAMILY_15_SUPPORT FALSE
 
-/*	Select the cpu socket type.	*/
+/* Select the cpu socket type. */
 #define INSTALL_G34_SOCKET_SUPPORT	FALSE
 #define INSTALL_C32_SOCKET_SUPPORT	FALSE
 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
@@ -69,8 +68,8 @@
 #define INSTALL_FT1_SOCKET_SUPPORT	TRUE
 #define INSTALL_AM3_SOCKET_SUPPORT	FALSE
 
-/*
- * Agesa optional capabilities selection.
+/**
+ * AGESA optional capabilities selection.
  * Uncomment and mark FALSE those features you wish to include in the build.
  * Comment out or mark TRUE those features you want to REMOVE from the build.
  */
@@ -102,13 +101,13 @@
 #define BLDOPT_REMOVE_DQS_TRAINING				FALSE
 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
-#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
-	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
-	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
+		#define BLDOPT_REMOVE_ACPI_PSTATES				FALSE
+		#define BLDCFG_REMOVE_ACPI_PSTATES_PPC			FALSE
+		#define BLDCFG_REMOVE_ACPI_PSTATES_PCT			FALSE
+		#define BLDCFG_REMOVE_ACPI_PSTATES_PSD			FALSE
+		#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
+		#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
+		#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
 #define BLDOPT_REMOVE_SRAT						FALSE
 #define BLDOPT_REMOVE_SLIT						FALSE
 #define BLDOPT_REMOVE_WHEA						FALSE
@@ -123,7 +122,7 @@
 #define BLDOPT_REMOVE_EARLY_SAMPLES				TRUE
 
 /*
- * Agesa entry points used in this implementation.
+ * AGESA entry points used in this implementation.
  */
 #define AGESA_ENTRY_INIT_RESET					TRUE
 #define AGESA_ENTRY_INIT_RECOVERY				FALSE
@@ -233,8 +232,8 @@
 #define BLDCFG_HEAP_DRAM_ADDRESS				0xB0000
 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS	0xD0000000
 
-/*
- * Agesa configuration values selection.
+/**
+ * AGESA configuration values selection.
  * Uncomment and specify the value for the configuration options
  * needed by the system.
  */
@@ -256,8 +255,8 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 	{ CPU_LIST_TERMINAL }
 };
 
-/*****************************************************************************
- *	 Define the RELEASE VERSION string
+/**
+ * @brief Define the RELEASE VERSION string
  *
  * The Release Version string should identify the next planned release.
  * When a branch is made in preparation for a release, the release manager
@@ -268,42 +267,48 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  * The release manager will need to remove the trailing 'X' and update the
  * version string as appropriate for the release. The trunk copy of this file
  * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
-// This is the delivery package title, "BrazosPI"
-// This string MUST be exactly 8 characters long
+ */
+
+/*
+ * This is the delivery package title, "BrazosPI"
+ * This string MUST be exactly 8 characters long
+ */
 #define AGESA_PACKAGE_STRING	{'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 
-// This is the release version number of the AGESA component
-// This string MUST be exactly 12 characters long
+/* This is the release version number of the AGESA component
+ * This string MUST be exactly 12 characters long
+ */
 #define AGESA_VERSION_STRING	{'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
 
 /* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY				200 ///< DDR 400
-#define DDR533_FREQUENCY				266 ///< DDR 533
-#define DDR667_FREQUENCY				333 ///< DDR 667
-#define DDR800_FREQUENCY				400 ///< DDR 800
-#define DDR1066_FREQUENCY				533 ///< DDR 1066
-#define DDR1333_FREQUENCY				667 ///< DDR 1333
-#define DDR1600_FREQUENCY				800 ///< DDR 1600
-#define DDR1866_FREQUENCY				933 ///< DDR 1866
-#define UNSUPPORTED_DDR_FREQUENCY		934 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY				200 /**< DDR 400 */
+#define DDR533_FREQUENCY				266 /**< DDR 533 */
+#define DDR667_FREQUENCY				333 /**< DDR 667 */
+#define DDR800_FREQUENCY				400 /**< DDR 800 */
+#define DDR1066_FREQUENCY				533 /**< DDR 1066 */
+#define DDR1333_FREQUENCY				667 /**< DDR 1333 */
+#define DDR1600_FREQUENCY				800 /**< DDR 1600 */
+#define DDR1866_FREQUENCY				933 /**< DDR 1866 */
+#define UNSUPPORTED_DDR_FREQUENCY		934 /**< Max limit of DDR frequency */
 
 /* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED				0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED				1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED				0 /**< Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED				1 /**< Quadrank unbuffered DIMM */
 
 /* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO				0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED				1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC			2 ///< Set user specified speed
+#define TIMING_MODE_AUTO				0 /**< Use best rate possible */
+#define TIMING_MODE_LIMITED				1 /**< Set user top limit */
+#define TIMING_MODE_SPECIFIC			2 /**< Set user specified speed */
 
 /* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL			0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT		1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL			0 /**< Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT		1 /**< Chip select power down mode */
 
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file.	The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/**
+ * The following definitions specify the default values for various parameters
+ * in which there are no clearly defined defaults to be used in the common
+ * file. The values below are based on product and BKDG content.
+ */
 #define DFLT_SCRUB_DRAM_RATE			(0)
 #define DFLT_SCRUB_L2_RATE				(0)
 #define DFLT_SCRUB_L3_RATE				(0)
@@ -316,121 +321,25 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 /* Instantiate all solution relevant data. */
 #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
 
-/*----------------------------------------------------------------------------------------
- *						CUSTOMER OVERIDES MEMORY TABLE
- *----------------------------------------------------------------------------------------
- */
-
-/*
- *	Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *	(e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *	is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *	use its default conservative settings.
+/**
+ * @brief Customer Overides Memory Table
+ *
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform
+ * information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...).
+ * If PlatformSpecificTable is populated, AGESA will base its settings on the
+ * data from the table. Otherwise, it will use its default conservative settings.
  */
 const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-	//
-	// The following macros are supported (use comma to separate macros):
-	//
-	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-	//			The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-	//			AGESA will base on this value to disable unused MemClk to save power.
-	//			Example:
-	//			BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-	//					 Bit AM3/S1g3 pin name
-	//					 0	 M[B,A]_CLK_H/L[0]
-	//					 1	 M[B,A]_CLK_H/L[1]
-	//					 2	 M[B,A]_CLK_H/L[2]
-	//					 3	 M[B,A]_CLK_H/L[3]
-	//					 4	 M[B,A]_CLK_H/L[4]
-	//					 5	 M[B,A]_CLK_H/L[5]
-	//					 6	 M[B,A]_CLK_H/L[6]
-	//					 7	 M[B,A]_CLK_H/L[7]
-	//			And platform has the following routing:
-	//					 CS0	 M[B,A]_CLK_H/L[4]
-	//					 CS1	 M[B,A]_CLK_H/L[2]
-	//					 CS2	 M[B,A]_CLK_H/L[3]
-	//					 CS3	 M[B,A]_CLK_H/L[5]
-	//			Then platform can specify the following macro:
-	//			MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-	//
-	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-	//			The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-	//			AGESA will base on this value to tristate unused CKE to save power.
-	//
-	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-	//			The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-	//			AGESA will base on this value to tristate unused ODT pins to save power.
-	//
-	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-	//			The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-	//			AGESA will base on this value to tristate unused Chip select to save power.
-	//
-	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-	//			Specifies the number of DIMM slots per channel.
-	//
-	// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-	//			Specifies the number of Chip selects per channel.
-	//
-	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-	//			Specifies the number of channels per socket.
-	//
-	// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-	//			Specifies DDR bus speed of channel ChannelID on socket SocketID.
-	//
-	// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-	//			Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-	//
-	// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-	//			Byte6Seed, Byte7Seed, ByteEccSeed)
-	//			Specifies the write leveling seed for a channel of a socket.
-	//
 	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
 	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
 	PSO_END
 };
 
 
-//DA Customer table
+/* DA Customer table */
 const uint8_t AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
 {
- // Hardcoded Memory Training Values
-
- // The following macro should be used to override training values for your platform
- //
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
- //
- //	 NOTE:
- //	 The following training hardcode values are example values that were taken from a tilapia motherboard
- //	 with a particular DIMM configuration.	To hardcode your own values, uncomment the appropriate line in
- //	 the table and replace the byte lane values with your own.
- //
- //	 ------------------ BYTE LANES ----------------------
- //	BL0	 BL1	 BL2	 BL3	 BL4	 BL5	 BL6	 Bl7	 ECC
- // Write Data Timing
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
-
- // DQS Receiver Enable
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
-
- // Write DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
-
- // Read DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
- //--------------------------------------------------------------------------------------------------------------------------------------------------
- // TABLE END
-	NBACCESS (MTEnd, 0,	0, 0, 0, 0),			// End of Table
+	NBACCESS (MTEnd, 0,	0, 0, 0, 0), /* End of Table */
 };
 const uint8_t SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index 1491f29970..8fb079537c 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -30,18 +30,19 @@
 #include <southbridge/amd/cimx/sb800/sb_cimx.h>
 
 
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
+/**
+ * Global variables for mainboard layouts. These are shared by irqtable,
+ * mptable and acpi_tables where busnum is default.
+ */
 u8 bus_isa;
 u8 bus_sb800[6];
 u32 apicid_sb800;
 
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
+/**
+ * Here you only need to set value in pci1234 for HT-IO that could be
+ * installed or not. You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
 u32 pci1234x[] = {
 	0x0000ff0,
 };
@@ -53,7 +54,7 @@ static u32 get_bus_conf_done = 0;
 
 #if CONFIG_HAVE_ACPI_RESUME
 extern u8 acpi_slp_type;
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 void get_bus_conf(void)
 {
@@ -63,26 +64,31 @@ void get_bus_conf(void)
 	device_t dev;
 	int i, j;
 
+	/* Be sure func is called exactly once */
 	if (get_bus_conf_done == 1)
-		return;	 /* do it only once */
+		return;
 
 	get_bus_conf_done = 1;
 
-/*
- * This is the call to AmdInitLate.	It is really in the wrong place, conceptually,
- * but functionally within the coreboot model, this is the best place to make the
- * call.	The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM.	The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "main".	There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions.	The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written.	This routine is called at the beginning
- * of each of the write functions called prior to the ACPI write functions, so this
- * becomes the best place for this call.
- */
+	/*
+	 * This is the call to AmdInitLate. It is really in the wrong place,
+	 * conceptually, but functionally within the coreboot model, this is the
+	 * best place to make the call. The logically correct place to call
+	 * AmdInitLate is after PCI scan is done, after the decision about S3
+	 * resume is made, and before the system tables are written into RAM. The
+	 * routine that is
+	 * responsible for writing the tables is "write_tables", called near the
+	 * end of "main". There is no platform specific entry point between the S3
+	 * resume decision point and the call to "write_tables", and the next
+	 * platform specific entry points are the calls to the ACPI table write
+	 * functions. The first of ose would seem to be the right place, but other
+	 * table write
+	 * functions, e.g. the PIRQ table write function, are called before the
+	 * ACPI tables are written. This routine is called at the beginning of each
+	 * of the write functions called prior to the ACPI write functions, so this
+	 * becomes the best place for this call.
+	 */
+
 #if CONFIG_HAVE_ACPI_RESUME
 	if (acpi_slp_type != 3) {
 		status = agesawrapper_amdinitlate();
@@ -96,7 +102,8 @@ void get_bus_conf(void)
 	status = agesawrapper_amdinitlate();
 	if(status)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+
 	sbdn_sb800 = 0;
 
 	memset(bus_sb800, 0, sizeof(bus_sb800));
@@ -142,5 +149,5 @@ void get_bus_conf(void)
 
 #if CONFIG_AMD_SB_CIMX
 	sb_Late_Post();
-#endif
+#endif /* CONFIG_AMD_SB_CIMX */
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
index b77c375259..259034b524 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
@@ -26,9 +26,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+			u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
@@ -58,15 +58,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	u8 sum = 0;
 	int i;
 
+	/* Find all Bus num and APIC's that are share with
+	 * mptable.c and acpi_tables.c
+	 */
+	get_bus_conf();
 
-	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
 
-
-	/* Align the table to be 16 byte aligned. */
+	/* Align table on 16 byte boundary. */
 	addr += 15;
 	addr &= ~15;
 
-	/* This table must be betweeen 0xf0000 & 0x100000 */
+	/* This table must be between 0xf0000 & 0x100000 */
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
@@ -90,19 +92,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info = (void *)(&pirq->checksum + 1);
 	slot_num = 0;
 
-
-	/* pci bridge */
+	/* PCI Bridge */
 	write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
 			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
 			0);
 	pirq_info++;
 
-
-
 	slot_num++;
 
-
-
 	pirq->size = 32 + 16 * slot_num;
 
 	for (i = 0; i < pirq->size; i++)
@@ -117,5 +114,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
 
 	return (unsigned long)pirq_info;
-
 }
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index d5f2d03d4f..b3c9e3dc01 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -64,7 +64,7 @@ static void mainboard_enable(device_t dev)
  */
 #if CONFIG_HAVE_ACPI_RESUME
 	acpi_slp_type = acpi_get_sleep_type();
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 	/* enable GPP CLK0 thru CLK3 (interleaved) */
 	/* disable GPP CLK4 thru SLT_GFX_CLK */
@@ -77,7 +77,7 @@ static void mainboard_enable(device_t dev)
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
-	 * long ago set things up this way inside the SPD read code.  The
+	 * long ago set things up this way inside the SPD read code. The
 	 * SPD read code has been made generic and moved out of the board
 	 * directory, so the ASF init is being done here.
 	 */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index d7fe6a06d0..7a0872620a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -95,7 +95,6 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
 	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
 	PCI_INT(0x0, 0x14, 0x0, 0x10);
 	/* Southbridge HD Audio: */
 	PCI_INT(0x0, 0x14, 0x2, 0x12);
@@ -107,10 +106,10 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
 	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 
-	/* sata */
+	/* SATA */
 	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-	/* on board NIC & Slot PCIE.	*/
+	/* On-board NIC & Slot PCIE. */
 
 	/* PCI slots */
 	/* PCI_SLOT 0. */
@@ -119,7 +118,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
 	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
 
-	/* PCI_SLOT 1. */
+	/* On-board Realtek NIC 1. */
 	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
 	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
 	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
@@ -135,7 +134,7 @@ static void *smp_write_config_table(void *v)
 	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
 	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
-	/* PCIe PortA */
+	/* On-board Realtek NIC 2. (PCIe PortA) */
 	PCI_INT(0x0, 0x15, 0x0, 0x10);
 	/* PCIe PortB */
 	PCI_INT(0x0, 0x15, 0x1, 0x11);
@@ -144,7 +143,9 @@ static void *smp_write_config_table(void *v)
 	/* PCIe PortD */
 	PCI_INT(0x0, 0x15, 0x3, 0x13);
 
-	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
+	/* Local Ints:
+	 * Type | Polarity | Trigger | Bus ID | IRQ | APIC ID PIN#
+	 */
 	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 846d5c76f4..3406edfde9 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
 	}
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
 
 	/* Initialize i8259 pic */
 	post_code(0x43);