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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-27 13:32:59 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-07-03 09:50:41 +0200 |
| commit | 6a089e3b18ebb5561ae7233d28ff53fff9fbe676 (patch) | |
| tree | cb85377196643223de2d8977d32ccd6c1e4c0868 /src/mainboard/jetway | |
| parent | db8693bde7ad2cc2f6b32bb9654685c1ddb502b2 (diff) | |
| download | coreboot-6a089e3b18ebb5561ae7233d28ff53fff9fbe676.tar.xz | |
AGESA boards: Use acpi_is_wakeup_s3()
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6143
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index 56f6c43dfb..5f08149b10 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -157,14 +157,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); -/* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the appropriate AGESA/CIMx resume functions. - */ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = acpi_get_sleep_type(); -#endif /* CONFIG_HAVE_ACPI_RESUME */ - /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK4 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); |