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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-22 10:24:20 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-28 17:25:15 +0200
commitb426107d1db17b606a90be83ddd3bf8a1c0d8751 (patch)
tree0fa5addebf1993a25d8a74fd405bbf59c3def7f8 /src/mainboard/jetway
parentcdfb46240b4bba8a112c85a5f5d26447e90378b3 (diff)
downloadcoreboot-b426107d1db17b606a90be83ddd3bf8a1c0d8751.tar.xz
AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c17
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/mptable.c16
2 files changed, 11 insertions, 22 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index cc3ffbbeb6..2cfc5c699b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -33,14 +33,9 @@
* mptable and acpi_tables where busnum is default.
*/
u8 bus_sb800[6];
-u32 apicid_sb800;
-u32 apicver_sb800;
-
void get_bus_conf(void)
{
- u32 apicid_base;
-
device_t dev;
int i;
@@ -61,16 +56,4 @@ void get_bus_conf(void)
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
-
- /* I/O APICs: APIC ID Version State Address */
- apicid_base = CONFIG_MAX_CPUS;
-
- /*
- * By the time this function gets called, the IOAPIC registers
- * have been written so they can be read to get the correct
- * APIC ID and Version
- */
- apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
- apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
-
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
index b621dd200b..4390605e0d 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c
@@ -33,14 +33,20 @@
#include <southbridge/amd/amd_pci_util.h>
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-extern u32 apicid_sb800;
-extern u32 apicver_sb800;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF);
+
/* Intialize the MP_Table */
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -64,20 +70,20 @@ static void *smp_write_config_table(void *v)
* Type 2: I/O APICs:
* APIC ID, Version, APIC Flags:EN, Address
*/
- smp_write_ioapic(mc, apicid_sb800, apicver_sb800, IO_APIC_ADDR);
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/*
* Type 3: I/O Interrupt Table Entries:
* Int Type, Int Polarity, Int Level, Source Bus ID,
* Source Bus IRQ, Dest APIC ID, Dest PIN#
*/
- mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
/* APU Internal Graphic Device */
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);