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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-03 14:06:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-13 08:58:12 +0000 |
| commit | 3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09 (patch) | |
| tree | 98196a78b5aed35d8c238cfb6b86668506e526e5 /src/mainboard/jetway | |
| parent | 24f0455016720e4222057ecda3415c05c7cb095c (diff) | |
| download | coreboot-3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09.tar.xz | |
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock,
this call can be delayed to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index a971c15d52..5e61bddfcc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -17,11 +17,13 @@ #include <northbridge/amd/agesa/state_machine.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> +#include <sb_cimx.h> /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) void board_BeforeAgesa(struct sysinfo *cb) { + sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } |