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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-18 23:51:12 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-18 23:51:12 +0000 |
| commit | b3ae1867d1a4b495a56078f521bebec9981f7494 (patch) | |
| tree | 5f05b92696c5b38932c0bacfb00f5aff285d83f3 /src/mainboard/jetway | |
| parent | 261f842c1c3ce5e4ee151889f692a16856c400f3 (diff) | |
| download | coreboot-b3ae1867d1a4b495a56078f521bebec9981f7494.tar.xz | |
* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value
to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/jetway')
| -rw-r--r-- | src/mainboard/jetway/pa78vm5/romstage.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 05b0e8b40a..3fd3972559 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -112,13 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) f71863fg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); -#if CONFIG_USBDEBUG - sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); - early_usbdebug_init(); -#endif - console_init(); - printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |