summaryrefslogtreecommitdiff
path: root/src/mainboard/jetway
diff options
context:
space:
mode:
authorStefan Reinauer <reinauer@chromium.org>2015-07-30 11:16:37 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-10-30 18:31:35 +0100
commitdd132a5d2d58ba011d535ae86a18e166d0cf5818 (patch)
treeb6877047805a6916a6b7583a2b7cd2aff5c8580b /src/mainboard/jetway
parent5fa4cb6d32b469ef8312de0c12ec648c085b9a1f (diff)
downloadcoreboot-dd132a5d2d58ba011d535ae86a18e166d0cf5818.tar.xz
AMD mainboards: Fix 64bit BiosCallOuts.c
Change-Id: I0f3297dff47dfb44da034ac6f305dcf1981b9de1 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/jetway')
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
index 1f14ad4431..11935a4c42 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c
@@ -26,8 +26,8 @@
#include <stdint.h>
#include <stdlib.h>
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
@@ -44,7 +44,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
/* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
* Make sure the right speed settings are selected.
@@ -54,7 +54,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config
}
/* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
uint32_t FcnData;