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| author | Puthikorn Voravootivat <puthik@chromium.org> | 2019-05-13 16:24:15 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:48:01 +0000 |
| commit | 111f9a9bcd710c3ee1ac89cf81b603a2de23cc62 (patch) | |
| tree | 53807c5f4158df39c1526026939d957999c9b418 /src/mainboard/jetway | |
| parent | 2968c9d6c7bff8d126aee6fba329ce92bd65c86e (diff) | |
| download | coreboot-111f9a9bcd710c3ee1ac89cf81b603a2de23cc62.tar.xz | |
mb/google/poppy/variants/atlas: Remove B0D4 _PSV
Per Intel, the internal thermal protection is working better
than putting B0D4 _PSV in dptf.
BUG=b:131251533
TEST=Get ~10% better Octane score.
Correct TCC and TCC offset in MSR register.
Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Diffstat (limited to 'src/mainboard/jetway')
0 files changed, 0 insertions, 0 deletions