diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-10-26 17:12:21 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2009-10-26 17:12:21 +0000 |
commit | aca6ec66bf7048e77ec960bb751a04e6b0528c70 (patch) | |
tree | f8fbc185686787e9453f0e6f229d88f38561333d /src/mainboard/kontron/986lcd-m/Config.lb | |
parent | 3b314023802c7429012e5f09652047e0b32fb97a (diff) | |
download | coreboot-aca6ec66bf7048e77ec960bb751a04e6b0528c70.tar.xz |
Kontron 986LCD-M update
- run ACPI code through preprocessor so we get the same values
as the C code
- fix PCIe x16 slot
- fix ICH7 Azalia/HDA driver
- SMI/GNVS update security fix (only allow struct pointer update once)
- ACPI updates
- IDE driver fixes
- add cmos options for disabling onboard ethernet and controlling system fan
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/Config.lb')
-rw-r--r-- | src/mainboard/kontron/986lcd-m/Config.lb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index 0dc004055c..eab88a9589 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -55,7 +55,8 @@ if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o makerule dsdt.c depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" + action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" + action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" action "mv $(CURDIR)/dsdt.hex dsdt.c" end object ./dsdt.o @@ -150,7 +151,8 @@ chip northbridge/intel/i945 device pci_domain 0 on device pci 00.0 on end # host bridge - device pci 01.0 off end # i945 PCIe root port + # autodetect 0:1.0 because it might or might not be there. + # device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller # register "rom_address" = "0xfffc0000" # 256 KB image @@ -174,6 +176,7 @@ chip northbridge/intel/i945 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" + register "gpe0_en" = "0x00000400" register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" |