diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-03-11 14:54:18 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2009-03-11 14:54:18 +0000 |
commit | a8e1168064b34b46494b58480411a11bc98340f6 (patch) | |
tree | 7d8c27e67ed67a3b96356581bad604b496f7cdd5 /src/mainboard/kontron/986lcd-m/Config.lb | |
parent | 6df0c62b688d1c4157bc151f98a2feeeca79fee8 (diff) | |
download | coreboot-a8e1168064b34b46494b58480411a11bc98340f6.tar.xz |
This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:
* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/Config.lb')
-rw-r--r-- | src/mainboard/kontron/986lcd-m/Config.lb | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index 3e378273c2..e5d110c130 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -190,12 +190,18 @@ chip northbridge/intel/i945 chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x06" + register "pirqc_routing" = "0x05" register "pirqd_routing" = "0x07" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x05" + register "pirqh_routing" = "0x06" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" |