diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/kontron/986lcd-m/romstage.c | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/romstage.c')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index d29b23bde7..5c7724828e 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -21,7 +21,7 @@ /* Configuration of the i945 driver */ #define CHIPSET_I945GM 1 -/* Usually system firmware turns off system memory clock signals to +/* Usually system firmware turns off system memory clock signals to * unused SO-DIMM slots to reduce EMI and power consumption. * However, the Kontron 986LCD-M does not like unused clock signals to * be disabled. If other similar mainboard occur, it would make sense @@ -107,7 +107,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); // COM4 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode + // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); } @@ -119,7 +119,7 @@ static void ich7_enable_lpc(void) static void early_superio_config_w83627thg(void) { device_t dev; - + dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_ext_func_mode(dev); @@ -194,7 +194,7 @@ static void early_superio_config_w83627thg(void) pnp_set_irq(dev, PNP_IDX_IRQ0, 11); pnp_set_enable(dev, 1); - dev=PNP_DEV(0x4e, W83627THG_SP2); + dev=PNP_DEV(0x4e, W83627THG_SP2); pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); @@ -249,7 +249,7 @@ static void rcba_config(void) * would essentially disable all three ethernet ports of the mainboard. * It's possible to rename the ports to achieve compatibility to the * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. + * interrupt routing information. * To avoid this, we enable (unused) port 6 and swap it with port 1 * in the case that ethernet port 1 is disabled. Since no devices * are connected to that port, we don't have to worry about interrupt @@ -413,7 +413,7 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); - + #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif @@ -423,8 +423,8 @@ void main(unsigned long bist) /* Perform some initialization that must run before stage2 */ early_ich7_init(); - /* This should probably go away. Until now it is required - * and mainboard specific + /* This should probably go away. Until now it is required + * and mainboard specific */ rcba_config(); @@ -470,7 +470,7 @@ void main(unsigned long bist) * memory completely, but that's a wonderful clean up task for another * day. */ - if (resume_backup_memory) + if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); /* Magic for S3 resume */ |