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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 23:48:42 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:46:18 +0000 |
commit | c583920a748fb8bd7999142433ad08641b06283d (patch) | |
tree | ac67268b34fed71bbf5f2915e6da0860151e60ee /src/mainboard/kontron/986lcd-m/romstage.c | |
parent | e27c013f39f0433dac57a754b3484553a536f30d (diff) | |
download | coreboot-c583920a748fb8bd7999142433ad08641b06283d.tar.xz |
nb/intel/i945: Initialize console in bootblock
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m/romstage.c')
-rw-r--r-- | src/mainboard/kontron/986lcd-m/romstage.c | 161 |
1 files changed, 0 insertions, 161 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c deleted file mode 100644 index 2c894534f3..0000000000 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <device/pnp_ops.h> -#include <device/pnp_def.h> -#include <pc80/mc146818rtc.h> -#include <northbridge/intel/i945/i945.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627thg/w83627thg.h> - -#include "option_table.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) - lpt_en = LPT_LPC_EN; /* enable LPT */ - - pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); -} - -/* This box has two superios, so enabling serial becomes slightly excessive. - * We disable a lot of stuff to make sure that there are no conflicts between - * the two. Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_enter_conf_state(dev); - - pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ - - pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ - pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ - - dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); /* Just enable it */ - - dev = PNP_DEV(0x2e, W83627THG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ - pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ - - dev = PNP_DEV(0x2e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x2e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - /* Enable HWM */ - dev = PNP_DEV(0x2e, W83627THG_HWM); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); - - dev = PNP_DEV(0x4e, W83627THG_SP1); - pnp_enter_conf_state(dev); - - pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 11); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 10); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); - - pnp_exit_conf_state(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(D28IP) = 0x00214321; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x3241; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3210; - RCBA16(D27IR) = 0x3210; - - /* Enable PCIe Root Port Clock Gate */ -} |