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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-21 18:35:37 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-01 01:54:08 +0000
commitdf128a55b183d3d7a6d7ae986f33abffac50f371 (patch)
tree66f2cef1c9f2516da2783cb945b99f8223e74046 /src/mainboard/kontron/986lcd-m
parenta84a7340b6291e209db2d5a3a28507816eec2223 (diff)
downloadcoreboot-df128a55b183d3d7a6d7ae986f33abffac50f371.tar.xz
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index bbaad83089..cee7c2a603 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -247,9 +247,9 @@ void mainboard_romstage_entry(void)
enable_lapic();
/* Force PCIRST# */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET);
udelay(200 * 1000);
- pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0);
ich7_enable_lpc();
early_superio_config_w83627thg();