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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-14 21:01:22 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-25 05:41:40 +0200
commit206f37043ed4c8581c7351399c267434653ec13b (patch)
treefda3d5fd1dcd136eeb36564a1ac1588601119e0f /src/mainboard/kontron/986lcd-m
parentbd4553bb4c594ff5098fc7c4c85133aab163705e (diff)
downloadcoreboot-206f37043ed4c8581c7351399c267434653ec13b.tar.xz
i945 boards: Drop disabled ram_check() calls
This code would not get enabled just by flipping the options in menuconfig, also ramcheck() no longer test the range like the parameters would imply. We should add non-destructive ram_check() on S3 resume path to verify memory controller configuration has been properly recovered. Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6027 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 06a74c420c..9c76a420ba 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -402,23 +402,6 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if !CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG_DEBUG_RAM_SETUP
- sdram_dump_mchbar_registers();
-#endif
-
- {
- /* This will not work if TSEG is in place! */
- u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
-
- printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
- ram_check(0x00000000, 0x000a0000);
- //ram_check(0x00100000, tom);
- }
-#endif
-#endif
-
quick_ram_check();
MCHBAR16(SSKPD) = 0xCAFE;