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authorArthur Heymans <arthur@aheymans.xyz>2019-11-09 14:19:04 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:22:57 +0000
commitfecf77770b8e68b9ef82021ca53c31db93736d93 (patch)
tree001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/kontron/986lcd-m
parent675cb9152e6704383cf402c55758ddea2c7a1e05 (diff)
downloadcoreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/kontron/986lcd-m')
-rw-r--r--src/mainboard/kontron/986lcd-m/devicetree.cb5
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c23
2 files changed, 10 insertions, 18 deletions
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb
index e2c0d88a0a..741c47b8f9 100644
--- a/src/mainboard/kontron/986lcd-m/devicetree.cb
+++ b/src/mainboard/kontron/986lcd-m/devicetree.cb
@@ -39,6 +39,11 @@ chip northbridge/intel/i945
register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "0"
+ register "gen1_dec" = "0x00fc0a01" # HWM
+ register "gen2_dec" = "0x000403e9" # COM3
+ register "gen3_dec" = "0x000402e9" # COM4
+ register "gen4_dec" = "0x00000301" # ??
+
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 229e3594c8..cb01046010 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -34,28 +34,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-static void ich7_enable_lpc(void)
+/* Override the default lpc decode ranges */
+static void mb_lpc_decode(void)
{
int lpt_en = 0;
if (read_option(lpt, 0) != 0)
lpt_en = LPT_LPC_EN; /* enable LPT */
- /* Enable Serial IRQ */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
- /* Set COM1/COM2 decode range */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010);
- /* Enable COM1/COM2/KBD/SuperIO1+2 */
- pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
- | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN
- | COMB_LPC_EN | lpt_en);
- /* Enable HWM at 0xa00 */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01);
- /* COM3 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9);
- /* COM4 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9);
- /* io 0x300 decode */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301);
+ pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
}
/* This box has two superios, so enabling serial becomes slightly excessive.
@@ -221,7 +207,8 @@ void mainboard_romstage_entry(void)
enable_lapic();
- ich7_enable_lpc();
+ i82801gx_lpc_setup();
+ mb_lpc_decode();
early_superio_config_w83627thg();
/* Set up the console */