mainboard/kontron: Use C89 comments style & remove commented code

Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16908
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 63 insertions, 76 deletions

diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c
index 0c5f403f46..fc67c22ea7 100644
--- a/src/mainboard/kontron/986lcd-m/irq_tables.c
+++ b/src/mainboard/kontron/986lcd-m/irq_tables.c
@@ -29,22 +29,22 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	0xf,		 /* u8 checksum. */
 	{
 		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA
-		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC
-		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, // USB#1
-		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Audio device
-		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, // PCIe bridge
-		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // Firewire
-		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, // PCI Bridge
+		{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* PCIe? */
+		{0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* VGA */
+		{0x00,(0x1e << 3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* PCI bridge */
+		{0x00,(0x1f << 3)|0x0, {{0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* LPC */
+		{0x00,(0x1d << 3)|0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x60, 0x0dcf8}}, 0x0, 0x0}, /* USB#1 */
+		{0x00,(0x1b << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Audio device */
+		{0x00,(0x1c << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x2, 0x0}, /* PCIe bridge */
+		{0x04,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* Firewire */
+		{0x04,(0x01 << 3)|0x0, {{0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x1, 0x0}, /* PCI Bridge */
 		{0x04,(0x02 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x2, 0x0},
 		{0x04,(0x03 << 3)|0x0, {{0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0x0dcf8}}, 0x3, 0x0},
 		{0x04,(0x04 << 3)|0x0, {{0x6b, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0x0dcf8}}, 0x4, 0x0},
 		{0x04,(0x05 << 3)|0x0, {{0x63, 0xdcd8}, {0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0x0dcf8}}, 0x5, 0x0},
 		{0x04,(0x06 << 3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x60, 0xdcf8}, {0x63, 0x0dcd8}}, 0x6, 0x0},
 		{0x04,(0x09 << 3)|0x0, {{0x69, 0xdcf8}, {0x6a, 0xdcf8}, {0x6b, 0xdcf8}, {0x68, 0x0dcf8}}, 0x9, 0x0},
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168
+		{0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, /* Ethernet 8168 */
 		{0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0},
 		{0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0},
 	}
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index 2a0c1470e2..d729533792 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -41,15 +41,15 @@ static void hwm_bank(u8 bank)
 #define FAN_CRUISE_CONTROL_THERMAL	2
 
 #define FAN_SPEED_5625	0
-//#define FAN_TEMPERATURE_30DEGC	0
+
 
 struct fan_speed {
 	u8 fan_in;
 	u16 fan_speed;
 };
 
-// FANIN Target Speed Register
-// FANIN = 337500 / RPM
+/* FANIN Target Speed Register */
+/* FANIN = 337500 / RPM */
 struct fan_speed fan_speeds[] = {
 	{ 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 },
 	{ 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 },
@@ -79,34 +79,27 @@ static void hwm_setup(void)
 	get_option(&cpufan_control, "cpufan_cruise_control");
 	cpufan_speed = FAN_SPEED_5625;
 	get_option(&cpufan_speed, "cpufan_speed");
-	//cpufan_temperature = FAN_TEMPERATURE_30DEGC;
-	//get_option(&cpufan_temperature, "cpufan_temperature");
 
 	sysfan_control = FAN_CRUISE_CONTROL_DISABLED;
 	get_option(&sysfan_control, "sysfan_cruise_control");
 	sysfan_speed = FAN_SPEED_5625;
 	get_option(&sysfan_speed, "sysfan_speed");
-	//sysfan_temperature = FAN_TEMPERATURE_30DEGC;
-	//get_option(&sysfan_temperature, "sysfan_temperature");
-
-	// hwm_write(0x31, 0x20); // AVCC high limit
-	// hwm_write(0x34, 0x06); // VIN2 low limit
 
 	hwm_bank(0);
-	hwm_write(0x59, 0x20); // Diode Selection
-	hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor
+	hwm_write(0x59, 0x20); /* Diode Selection */
+	hwm_write(0x5d, 0x0f); /* All Sensors Diode, not Thermistor */
 
 	hwm_bank(4);
-	hwm_write(0x54, 0xf1); // SYSTIN temperature offset
-	hwm_write(0x55, 0x19); // CPUTIN temperature offset
-	hwm_write(0x56, 0xfc); // AUXTIN temperature offset
+	hwm_write(0x54, 0xf1); /* SYSTIN temperature offset */
+	hwm_write(0x55, 0x19); /* CPUTIN temperature offset */
+	hwm_write(0x56, 0xfc); /* AUXTIN temperature offset */
 
-	hwm_bank(0x80); // Default
+	hwm_bank(0x80); /* Default */
 
 	u8 fan_config = 0;
-	// 00 FANOUT is Manual Mode
-	// 01 FANOUT is Thermal Cruise Mode
-	// 10 FANOUT is Fan Speed Cruise Mode
+	/* 00 FANOUT is Manual Mode */
+	/* 01 FANOUT is Thermal Cruise Mode */
+	/* 10 FANOUT is Fan Speed Cruise Mode */
 	switch (cpufan_control) {
 	case FAN_CRUISE_CONTROL_SPEED:	 fan_config |= (2 << 4); break;
 	case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break;
@@ -115,20 +108,20 @@ static void hwm_setup(void)
 	case FAN_CRUISE_CONTROL_SPEED:	 fan_config |= (2 << 2); break;
 	case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break;
 	}
-	// This register must be written first
+	/* This register must be written first */
 	hwm_write(0x04, fan_config);
 
 	switch (cpufan_control) {
 	case FAN_CRUISE_CONTROL_SPEED:
 		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n",
 				fan_speeds[cpufan_speed].fan_speed);
-		hwm_write(0x06, fan_speeds[cpufan_speed].fan_in);  // CPUFANIN target speed
+		hwm_write(0x06, fan_speeds[cpufan_speed].fan_in);  /* CPUFANIN target speed */
 		break;
 	case FAN_CRUISE_CONTROL_THERMAL:
 		printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n",
 				temperatures[cpufan_temperature].deg_celsius,
 				temperatures[cpufan_temperature].deg_fahrenheit);
-		hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius);  // CPUFANIN target temperature
+		hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius);  /* CPUFANIN target temperature */
 		break;
 	}
 
@@ -136,29 +129,27 @@ static void hwm_setup(void)
 	case FAN_CRUISE_CONTROL_SPEED:
 		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n",
 				fan_speeds[sysfan_speed].fan_speed);
-		hwm_write(0x05, fan_speeds[sysfan_speed].fan_in);  // SYSFANIN target speed
+		hwm_write(0x05, fan_speeds[sysfan_speed].fan_in);  /* SYSFANIN target speed */
 		break;
 	case FAN_CRUISE_CONTROL_THERMAL:
 		printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n",
 				temperatures[sysfan_temperature].deg_celsius,
 				temperatures[sysfan_temperature].deg_fahrenheit);
-		hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature
+		hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); /* SYSFANIN target temperature */
 		break;
 	}
 
-	hwm_write(0x0e, 0x02); // Fan Output Step Down Time
-	hwm_write(0x0f, 0x02); // Fan Output Step Up Time
+	hwm_write(0x0e, 0x02); /* Fan Output Step Down Time */
+	hwm_write(0x0f, 0x02); /* Fan Output Step Up Time */
 
-	hwm_write(0x47, 0xaf); // FAN divisor register
-	hwm_write(0x4b, 0x84); // AUXFANIN speed divisor
+	hwm_write(0x47, 0xaf); /* FAN divisor register */
+	hwm_write(0x4b, 0x84); /* AUXFANIN speed divisor */
 
-	hwm_write(0x40, 0x01); // Init, but no SMI#
+	hwm_write(0x40, 0x01); /* Init, but no SMI# */
 }
 
-
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
+/* mainboard_enable is executed as first thing after */
+/* enumerate_buses(). */
 
 static void mainboard_enable(device_t dev)
 {
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index 2ee28906d3..7db977d136 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -39,8 +39,8 @@ static void *smp_write_config_table(void *v)
 		firewire_bus = firewire->bus->secondary;
 	}
 
-	// If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
-	// highest bus number on the pci bus.
+	/* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
+	/* highest bus number on the pci bus. */
 	riser = dev_find_device(0x3388, 0x0021, 0);
 	if (!riser)
 		riser = dev_find_device(0x3388, 0x0022, 0);
@@ -77,11 +77,11 @@ static void *smp_write_config_table(void *v)
 
 	if (riser) {
 		/* Old riser card */
-		// riser slot top 5:8.0
+		/* riser slot top 5:8.0 */
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x20, ioapic_id, 0x14);
-		// riser slot middle 5:9.0
+		/* riser slot middle 5:9.0 */
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x24, ioapic_id, 0x15);
-		// riser slot bottom 5:a.0
+		/* riser slot bottom 5:a.0 */
 		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, riser_bus, 0x28, ioapic_id, 0x16);
 
 		/* New Riser Card */
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index e9143a84e3..e3063b2ce0 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
 
 #include <stdint.h>
 #include <string.h>
@@ -57,21 +57,21 @@ static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;
 	if (read_option(lpt, 0) != 0) {
-		lpt_en = 1 << 2; // enable LPT
+		lpt_en = 1 << 2; /* enable LPT */
 	}
-	// Enable Serial IRQ
+	/* Enable Serial IRQ */
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
-	// Set COM1/COM2 decode range
+	/* Set COM1/COM2 decode range */
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
-	// Enable COM1/COM2/KBD/SuperIO1+2
+	/* Enable COM1/COM2/KBD/SuperIO1+2 */
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en);
-	// Enable HWM at 0xa00
+	/* Enable HWM at 0xa00 */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01);
-	// COM3 decode
+	/* COM3 decode */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
-	// COM4 decode
+	/* COM4 decode */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
-	// io 0x300 decode
+	/* io 0x300 decode */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
 }
 
@@ -101,10 +101,10 @@ static void early_superio_config_w83627thg(void)
 	dev = PNP_DEV(0x2e, W83627THG_SP1);
 	pnp_enter_func_mode(dev);
 
-	pnp_write_config(dev, 0x24, 0xc6); // PNPCSV
+	pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */
 
-	pnp_write_config(dev, 0x29, 0x43); // GPIO settings
-	pnp_write_config(dev, 0x2a, 0x40); // GPIO settings
+	pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */
+	pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */
 
 	dev = PNP_DEV(0x2e, W83627THG_SP1);
 	pnp_set_logical_device(dev);
@@ -118,7 +118,6 @@ static void early_superio_config_w83627thg(void)
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 	pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
-	// pnp_write_config(dev, 0xf1, 4); // IRMODE0
 	pnp_set_enable(dev, 1);
 
 	dev = PNP_DEV(0x2e, W83627THG_KBC);
@@ -126,25 +125,24 @@ static void early_superio_config_w83627thg(void)
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 	pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
-	// pnp_write_config(dev, 0xf0, 0x82);
 	pnp_set_enable(dev, 1);
 
 	dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
-	pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
+	pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */
 	pnp_set_enable(dev, 1);
 
 	dev = PNP_DEV(0x2e, W83627THG_GPIO2);
 	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 1); // Just enable it
+	pnp_set_enable(dev, 1); /* Just enable it */
 
 	dev = PNP_DEV(0x2e, W83627THG_GPIO3);
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
-	pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
-	pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
-	pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
+	pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */
+	pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */
+	pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */
 
 	dev = PNP_DEV(0x2e, W83627THG_FDC);
 	pnp_set_logical_device(dev);
@@ -166,14 +164,14 @@ static void early_superio_config_w83627thg(void)
 	dev = PNP_DEV(0x4e, W83627THG_SP1);
 	pnp_enter_func_mode(dev);
 
-	pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
+	pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
 	pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
 	pnp_set_enable(dev, 1);
 
 	dev = PNP_DEV(0x4e, W83627THG_SP2);
-	pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
+	pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
 	pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
@@ -201,8 +199,6 @@ static void rcba_config(void)
 	u32 reg32;
 
 	/* Set up virtual channel 0 */
-	//RCBA32(0x0014) = 0x80000001;
-	//RCBA32(0x001c) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
 	RCBA32(0x3100) = 0x00042210;
@@ -267,7 +263,7 @@ static void rcba_config(void)
 	RCBA32(0x3418) = reg32;
 
 	/* Enable PCIe Root Port Clock Gate */
-	// RCBA32(0x341c) = 0x00000001;
+
 }
 
 static void early_ich7_init(void)
@@ -275,15 +271,15 @@ static void early_ich7_init(void)
 	uint8_t reg8;
 	uint32_t reg32;
 
-	// program secondary mlt XXX byte?
+	/* program secondary mlt XXX byte? */
 	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 
-	// reset rtc power status
+	/* reset rtc power status */
 	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 	reg8 &= ~(1 << 2);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 
-	// usb transient disconnect
+	/* usb transient disconnect */
 	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 	reg8 |= (3 << 0);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
@@ -317,7 +313,7 @@ static void early_ich7_init(void)
 	RCBA32(0x3e0e) |= (1 << 7);
 	RCBA32(0x3e4e) |= (1 << 7);
 
-	// next step only on ich7m b0 and later:
+	/* next step only on ich7m b0 and later: */
 	reg32 = RCBA32(0x2034);
 	reg32 &= ~(0x0f << 16);
 	reg32 |= (5 << 16);