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author | Nico Huber <nico.huber@secunet.com> | 2017-04-20 15:36:46 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2020-08-04 15:20:19 +0000 |
commit | 0ccfa6805fc453b581ae3fa3306655ef1a4c3e95 (patch) | |
tree | a6b79b9b7d93bc786b2077403dc846b044bbcb76 /src/mainboard/kontron/bsl6/romstage.c | |
parent | e0e28908d27451e85339d24f1fcf96091a1cd168 (diff) | |
download | coreboot-0ccfa6805fc453b581ae3fa3306655ef1a4c3e95.tar.xz |
mb/kontron/bsl6: Add new Skylake COMe module
Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the
bSL6.
The plain bSL6 variant received little testing and only during early
development. The Boxer26 variant is actively used and fully tested.
The latest rebase was boot tested with FILO and Linux 4.19.
Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29480
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/kontron/bsl6/romstage.c')
-rw-r--r-- | src/mainboard/kontron/bsl6/romstage.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c new file mode 100644 index 0000000000..9d9169c0d2 --- /dev/null +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <spd_bin.h> +#include <soc/romstage.h> +#include <fsp/soc_binding.h> +#include <pc80/mc146818rtc.h> + +#include "variant.h" + +/* Rcomp resistor */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp target */ +static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; + + get_option(&memory_params->HyperThreading, "hyper_threading"); + + variant_memory_init_params(mupd); +} |