kontron/ktqm77: New board

Change-Id: Ife1c0a8597c2de04773899cdd87af6b6c630906a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3392
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

6 files changed, 280 insertions, 0 deletions

diff --git a/src/mainboard/kontron/ktqm77/acpi/ec.asl b/src/mainboard/kontron/ktqm77/acpi/ec.asl
new file mode 100644
index 0000000000..7925e0db67
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/ec.asl
@@ -0,0 +1,7 @@
+#define IT8516E_EC_DEV		EC0
+#define SUPERIO_PNP_BASE	0x20e
+#define IT8516E_FIRST_DATA	0x62
+#define IT8516E_FIRST_SC	0x66
+#define IT8516E_SECOND_DATA	0x20c
+#define IT8516E_SECOND_SC	0x20d
+#include <ec/kontron/it8516e/acpi/ec.asl>
diff --git a/src/mainboard/kontron/ktqm77/acpi/mainboard.asl b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl
new file mode 100644
index 0000000000..10b1c1108a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (PWRB)
+	{
+		Name (_HID, EisaId("PNP0C0C"))
+	}
+}
diff --git a/src/mainboard/kontron/ktqm77/acpi/platform.asl b/src/mainboard/kontron/ktqm77/acpi/platform.asl
new file mode 100644
index 0000000000..ff6d94d05a
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/platform.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..b93aa96569
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Ivybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// LPC devices			0:1f.x
+							   //  D31IP_TTIP  THRT   INTC -> PIRQC
+			Package() { 0x001fffff, 2, 0, 18 },//  D31IP_SMIP  SMBUS  INTC -> PIRQC
+			Package() { 0x001fffff, 1, 0, 19 },//  D31IP_SIP   SATA   INTB -> PIRQD (MSI)
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 23 },//  D29IP_E1P   EHCI1  INTA -> PIRQH
+			// PCIe Root Ports		0:1c.x
+							   //  D28IP_P8IP  Slot?  INTD -> PIRQD
+			Package() { 0x001cffff, 3, 0, 19 },//  D28IP_P4IP  ETH2   INTD -> PIRQD (MSI)
+							   //  D28IP_P7IP  PCIEx1 INTC -> PIRQC
+			Package() { 0x001cffff, 2, 0, 18 },//  D28IP_P3IP  ETH1   INTC -> PIRQC (MSI)
+							   //  D28IP_P6IP  1394   INTB -> PIRQB (MSI)
+			Package() { 0x001cffff, 1, 0, 17 },//  D28IP_P2IP  Slot?  INTB -> PIRQB
+							   //  D28IP_P5IP  GbEPHY INTA -> PIRQA
+			Package() { 0x001cffff, 0, 0, 16 },//  D28IP_P1IP  Slot?  INTA -> PIRQA
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },//  D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 16 },//  D26IP_E2P   EHCI2  INTA -> PIRQA
+			// ETH0				0:19.0
+			Package() { 0x0019ffff, 0, 0, 20 },//  D25IP_LIP   ETH0   INTA -> PIRQE (MSI)
+			// xHCI				0:14.0
+			Package() { 0x0014ffff, 0, 0, 16 },//  D20IP_XHCIIP xHCI  INTA -> PIRQA (MSI)
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+			// PCIe PEG x16			0:1.0
+			Package() { 0x0001ffff, 3, 0, 19 },//              PEGx16 INTD -> PIRQD
+			Package() { 0x0001ffff, 2, 0, 18 },//              PEGx16 INTC -> PIRQC
+			Package() { 0x0001ffff, 1, 0, 17 },//              PEGx16 INTB -> PIRQB
+			Package() { 0x0001ffff, 0, 0, 16 },//              PEGx16 INTA -> PIRQA
+		})
+	} Else {
+		Return (Package() {
+			// LPC devices			0:1f.x
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// ETH0				0:19.0
+			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// xHCI				0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe PEG x16			0:1.0
+			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/kontron/ktqm77/acpi/superio.asl b/src/mainboard/kontron/ktqm77/acpi/superio.asl
new file mode 100644
index 0000000000..1ed4c931fc
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/superio.asl
@@ -0,0 +1,12 @@
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef W83627DHG_SHOW_UARTA
+#undef W83627DHG_SHOW_UARTB
+#undef W83627DHG_SHOW_KBC
+#undef W83627DHG_SHOW_PS2M
+#undef W83627DHG_SHOW_HWMON
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define W83627DHG_SHOW_UARTA	1
+#define W83627DHG_SHOW_UARTB	1
+#include <superio/winbond/w83627dhg/acpi/superio.asl>
diff --git a/src/mainboard/kontron/ktqm77/acpi/thermal.asl b/src/mainboard/kontron/ktqm77/acpi/thermal.asl
new file mode 100644
index 0000000000..093151a82e
--- /dev/null
+++ b/src/mainboard/kontron/ktqm77/acpi/thermal.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2013 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Return CPU Temperature from EC
+			Return (\_SB.PCI0.LPCB.EC0.PM1.CTK ())
+		}
+
+// The EC does all fan control. There is no Active Cooling Fan control (_ACx).
+	}
+}