diff options
author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-06-20 17:26:21 +0300 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:18:22 +0000 |
commit | 0fcd37172f22a55fecd5ae6752fc18218b88a8f3 (patch) | |
tree | 760464e8fd493cfe65e3efd4a0920937db506ab5 /src/mainboard/kontron/mal10/ramstage.c | |
parent | 0948b363b0568e70af2352566dee39e0df82d96d (diff) | |
download | coreboot-0fcd37172f22a55fecd5ae6752fc18218b88a8f3.tar.xz |
mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/kontron/mal10/ramstage.c')
-rw-r--r-- | src/mainboard/kontron/mal10/ramstage.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c new file mode 100644 index 0000000000..48194e6848 --- /dev/null +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <carrier/gpio.h> +#include <stddef.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + carrier_gpio_configure(); + + /* + * CPU Power Management Configuration correspond to the BIOS Setup menu settings + * in the AMI UEFI v112. + * TODO: move these FSP options to device tree + */ + silconfig->EnableCx = 1; /* Enable CPU power states */ + silconfig->C1e = 1; /* enable Enhanced C-states */ + /* + * Attention! Do not change PkgCStateLimit! This causes spikes in the power + * consumption of the SoC when the system comes out of power saving mode, and + * voltage sagging at the output of DC-DC converters on the COMe module. In the + * AMI BIOS Setup shows this parameter, but does not allow changing it. + */ + silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */ + silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */ + silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */ + silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */ + silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */ + silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */ + silconfig->PmSupport = 1; /* GT PM Support */ + silconfig->EnableRenderStandby = 1; /* enable render standby */ + silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */ + silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */ + + /* Override High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* Override APIC options */ + silconfig->IoApicId = 1; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; +} |