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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2020-06-20 17:26:21 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:18:22 +0000 |
commit | 0fcd37172f22a55fecd5ae6752fc18218b88a8f3 (patch) | |
tree | 760464e8fd493cfe65e3efd4a0920937db506ab5 /src/mainboard/kontron/mal10/romstage.c | |
parent | 0948b363b0568e70af2352566dee39e0df82d96d (diff) | |
download | coreboot-0fcd37172f22a55fecd5ae6752fc18218b88a8f3.tar.xz |
mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/kontron/mal10/romstage.c')
-rw-r--r-- | src/mainboard/kontron/mal10/romstage.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c new file mode 100644 index 0000000000..9f1d7eb87d --- /dev/null +++ b/src/mainboard/kontron/mal10/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <soc/romstage.h> +#include <FspmUpd.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.Profile = 0x19; + mupd->FspmConfig.MemoryDown = 0; + mupd->FspmConfig.DDR3LPageSize = 2; + mupd->FspmConfig.DualRankSupportEnable = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.DIMM0SPDAddress = 0xA0; + mupd->FspmConfig.DIMM1SPDAddress = 0xA4; + + mupd->FspmConfig.RmtCheckRun = 1; + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0; + mupd->FspmConfig.EnhancePort8xhDecoding = 1; + + mupd->FspmConfig.MsgLevelMask = 0; + mupd->FspmConfig.MrcDataSaving = 0; + mupd->FspmConfig.MrcFastBoot = 1; + + mupd->FspmConfig.PrimaryVideoAdaptor = 2; +} |