diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-11-06 17:11:05 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 17:11:05 +0000 |
| commit | d63085b20ef40caae1c60a7532b5243e1e30b109 (patch) | |
| tree | c732b7666d8082775022592eeddedff81375eeef /src/mainboard/kontron | |
| parent | eeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff) | |
| download | coreboot-d63085b20ef40caae1c60a7532b5243e1e30b109.tar.xz | |
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/kontron')
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/Config.lb | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/986lcd-m/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/kt690/Config.lb | 3 | ||||
| -rw-r--r-- | src/mainboard/kontron/kt690/devicetree.cb | 3 |
4 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb index eab88a9589..e89fc82c0e 100644 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ b/src/mainboard/kontron/986lcd-m/Config.lb @@ -155,9 +155,6 @@ chip northbridge/intel/i945 # device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 2a3615bf5d..8cd34b4f96 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -11,9 +11,6 @@ chip northbridge/intel/i945 device pci 01.0 off end # i945 PCIe root port chip drivers/pci/onboard device pci 02.0 on end # vga controller - # register "rom_address" = "0xfffc0000" # 256 KB image - # register "rom_address" = "0xfff80000" # 512 KB image - register "rom_address" = "0xfff00000" # 1 MB image end device pci 02.1 on end # display controller diff --git a/src/mainboard/kontron/kt690/Config.lb b/src/mainboard/kontron/kt690/Config.lb index f1b4215aa4..3a182b7ba9 100644 --- a/src/mainboard/kontron/kt690/Config.lb +++ b/src/mainboard/kontron/kt690/Config.lb @@ -134,7 +134,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,7 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -168,7 +166,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index e26350ccda..5983bbafd9 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,7 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -33,7 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" |