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authorPaul Menzel <paulepanter@users.sourceforge.net>2016-12-29 22:54:02 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-01-04 00:27:51 +0100
commit6c20b65849aeda664cc40ebc0f0bab2e99768423 (patch)
treee09bf7dbb67b69d46cb36444a7dc08e923053e5b /src/mainboard/kontron
parent68fdb785b2183cfa3312266b4a800174ba2d64e5 (diff)
downloadcoreboot-6c20b65849aeda664cc40ebc0f0bab2e99768423.tar.xz
intel/i945 boards: Add romstage time stamps
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/kontron')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index be51b7a3b2..e5fdc7318f 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -20,6 +20,7 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
+#include <timestamp.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
@@ -324,6 +325,10 @@ void mainboard_romstage_entry(unsigned long bist)
{
int s3resume = 0;
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
if (bist == 0)
enable_lapic();
@@ -361,7 +366,9 @@ void mainboard_romstage_entry(unsigned long bist)
dump_spd_registers();
#endif
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(s3resume ? 2 : 0, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
/* Perform some initialization that must run before stage2 */
early_ich7_init();