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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 17:22:00 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-21 00:39:47 +0200 |
| commit | 07921540dda79d810d8bfc6be211513c238a0d63 (patch) | |
| tree | 6395b9d31d8030480004a6af8f1afc12394f678f /src/mainboard/lanner/em8510 | |
| parent | 633c57d1d1ab3b2241fd259e12423054527ee000 (diff) | |
| download | coreboot-07921540dda79d810d8bfc6be211513c238a0d63.tar.xz | |
intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/lanner/em8510')
| -rw-r--r-- | src/mainboard/lanner/em8510/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 0a8c4d7cb5..2e5a125fb9 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -31,6 +31,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) @@ -42,8 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include <cpu/intel/romstage.h> -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) { #if 0 |