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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-16 23:15:37 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-16 23:15:37 +0000
commit2b6e93bd7ad11e7553e6cd220e1a5038930b09cb (patch)
tree9c31d397cfa1da9dd82a1acbae7474bec9db5bf6 /src/mainboard/lanner/em8510
parent3226cf8b9cff3dfeda64c189344baa239b375b6e (diff)
downloadcoreboot-2b6e93bd7ad11e7553e6cd220e1a5038930b09cb.tar.xz
Drop W83627THF, it's the same device as W83627THG.
The only difference is that the "G" version is in a Pb-free package, which is not relevant from a programmer's view. We keep W83627THG (and drop W83627THF) because: - The W83627THF had a CIR device / LDN which doesn't actually exist. - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out). - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards. This also fixes an issue on MSI MS7135's devicetree.cb: device pnp 4e.6 off end # XXX keep allocator happy The line above can be (and is) removed, as it was only needed due to the incorrect CIR LDN in the W83627THF. In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/lanner/em8510')
-rw-r--r--src/mainboard/lanner/em8510/Kconfig2
-rw-r--r--src/mainboard/lanner/em8510/devicetree.cb3
-rw-r--r--src/mainboard/lanner/em8510/romstage.c6
3 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/lanner/em8510/Kconfig b/src/mainboard/lanner/em8510/Kconfig
index b4d03f78eb..2ffdb842ea 100644
--- a/src/mainboard/lanner/em8510/Kconfig
+++ b/src/mainboard/lanner/em8510/Kconfig
@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_SOCKET_MPGA479M
select NORTHBRIDGE_INTEL_I855
select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_WINBOND_W83627THF
+ select SUPERIO_WINBOND_W83627THG
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_HARD_RESET
diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb
index 7df1443066..5784a16981 100644
--- a/src/mainboard/lanner/em8510/devicetree.cb
+++ b/src/mainboard/lanner/em8510/devicetree.cb
@@ -13,7 +13,7 @@ chip northbridge/intel/i855
register "enable_usb" = "0"
register "enable_native_ide" = "0"
device pci 1f.0 on
- chip superio/winbond/w83627thf # link 1
+ chip superio/winbond/w83627thg # link 1
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
@@ -37,7 +37,6 @@ chip northbridge/intel/i855
irq 0x70 = 1
irq 0x72 = 12
end
- device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c
index 6d79e0b3e5..fe4fd69327 100644
--- a/src/mainboard/lanner/em8510/romstage.c
+++ b/src/mainboard/lanner/em8510/romstage.c
@@ -34,11 +34,11 @@
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "northbridge/intel/i855/raminit.h"
#include "northbridge/intel/i855/debug.c"
-#include "superio/winbond/w83627thf/w83627thf_early_serial.c"
+#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -65,7 +65,7 @@ void main(unsigned long bist)
#endif
}
- w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();