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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-23 17:38:52 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-27 11:28:24 +0100
commit32960e30f08f678355b20b5702e8028351a7275e (patch)
tree8a44ac8674c02286bccb63bf8286645b3c3c367b /src/mainboard/lenovo/g505s/mainboard.c
parentb06eaf76b5142977aa130c22f09a97ad08bef036 (diff)
downloadcoreboot-32960e30f08f678355b20b5702e8028351a7275e.tar.xz
mainboard/lenovo/g505s: New port Richland APU A10-5750M
Richland APU A10-5750M 8GB RAM 4MB Flash Boots to working Linux with SeaBIOS payload. S3 works with Linux 3.16.3-2 Debian Jessie. Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7560 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/g505s/mainboard.c')
-rw-r--r--src/mainboard/lenovo/g505s/mainboard.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c
new file mode 100644
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--- /dev/null
+++ b/src/mainboard/lenovo/g505s/mainboard.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "ec.h"
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+#include <southbridge/amd/agesa/hudson/smi.h>
+
+
+static void pavilion_cold_boot_init(void)
+{
+ /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
+ hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW);
+ /* EC is not powered off during S3 sleep */
+ lenovo_g505s_ec_init();
+}
+
+static void mainboard_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
+ hudson_enable_smi_generation();
+
+ if (acpi_is_wakeup_s3())
+ agesawrapper_fchs3earlyrestore();
+ else
+ pavilion_cold_boot_init();
+
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};