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author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-23 17:38:52 +1100 |
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committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 11:28:24 +0100 |
commit | 32960e30f08f678355b20b5702e8028351a7275e (patch) | |
tree | 8a44ac8674c02286bccb63bf8286645b3c3c367b /src/mainboard/lenovo/g505s/romstage.c | |
parent | b06eaf76b5142977aa130c22f09a97ad08bef036 (diff) | |
download | coreboot-32960e30f08f678355b20b5702e8028351a7275e.tar.xz |
mainboard/lenovo/g505s: New port Richland APU A10-5750M
Richland APU A10-5750M
8GB RAM
4MB Flash
Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.
Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/g505s/romstage.c')
-rw-r--r-- | src/mainboard/lenovo/g505s/romstage.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c new file mode 100644 index 0000000000..01f463a0cb --- /dev/null +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper_call.h> + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/car.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <string.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + + hudson_lpc_port80(); + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x30); + + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + post_code(0x39); + + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + disable_cache_as_ram(); + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +} |