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authorAngel Pons <th3fanbus@gmail.com>2020-05-20 23:34:54 +0200
committerNico Huber <nico.h@gmx.de>2020-05-26 11:32:13 +0000
commit66ee42daba635a0748262092b28a3ee87bbfd573 (patch)
tree2bd3dc4ce21bfd183c66681d908fd1cd392288ff /src/mainboard/lenovo/g505s
parent927f6ae84a7b59b630250a7e559aac1eb05ae2f5 (diff)
downloadcoreboot-66ee42daba635a0748262092b28a3ee87bbfd573.tar.xz
mb/*/*/buildOpts.c: Clean up whitespace
Drop multiple blank lines and use one space inside C-style comments. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/mainboard/lenovo/g505s')
-rw-r--r--src/mainboard/lenovo/g505s/buildOpts.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index 6351aeedbb..bd7326dcd4 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -9,12 +9,10 @@
* build option selections desired for that platform.
*
* For Information about this file, see @ref platforminstall.
- *
*/
#include "mainboard.h"
-
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
/* Include the files that instantiate the configuration definitions. */
@@ -29,7 +27,6 @@
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
-
/* Select the CPU family. */
#define INSTALL_FAMILY_10_SUPPORT FALSE
#define INSTALL_FAMILY_12_SUPPORT FALSE
@@ -157,7 +154,7 @@
#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M */
#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
@@ -253,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DDR2400_FREQUENCY 1200 ///< DDR 2400
#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
-/* QUANDRANK_TYPE*/
+/* QUANDRANK_TYPE */
#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
@@ -339,7 +336,6 @@ GPIO_CONTROL lenovo_g505s_gpio[] = {
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&lenovo_g505s_gpio[0])
-
/* These definitions could be moved to a common Hudson header, should we decide
* to provide our own, saner SCI mapping function
*/