diff options
author | Tobias Diedrich <ranma+openocd@tdiedrich.de> | 2017-02-12 14:09:06 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2017-02-20 18:21:56 +0100 |
commit | cee930a39b183260ea83ac72fc9ca59d61353d8d (patch) | |
tree | b3fd18b7a202b837fc512e2b71a599956fdbbdee /src/mainboard/lenovo/s230u/smihandler.c | |
parent | 97535558f1a1c123a60d73244d835ff5d8d31213 (diff) | |
download | coreboot-cee930a39b183260ea83ac72fc9ca59d61353d8d.tar.xz |
lenovo/s230u: Add Thinkpad Twist (S230U)
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.
This model uses the same ENE KB9012 EC as the G505S.
Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works
Known issues:
- Patches needed for EC battery support
https://review.coreboot.org/#/c/18348/
https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
and needs to be reverse engineered.
Not tested:
- msata/wwan (probably works)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Reviewed-on: https://review.coreboot.org/18351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/s230u/smihandler.c')
-rw-r--r-- | src/mainboard/lenovo/s230u/smihandler.c | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c new file mode 100644 index 0000000000..755f176e91 --- /dev/null +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ec.h" + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <delay.h> +#include <ec/acpi/ec.h> +#include <ec/compal/ene932/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define GPE_PALMDET1 2 +#define GPE_PALMDET2 4 +#define GPE_EC_SCI 7 +#define GPE_EC_SMI 8 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +enum sleep_states { + S0 = 0, + S1 = 1, + S3 = 3, + S4 = 4, + S5 = 5, +}; + +enum ec_smi_event { + EC_SMI_EVENT_IDLE = 0x80, + EC_SMI_BATTERY_LOW = 0xb3, +}; + +/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs. */ +static void ec_enter_apm_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE9); +} +/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs. */ +static void ec_enter_acpi_mode(void) +{ + ec_kbc_write_cmd(0x59); + ec_kbc_write_ib(0xE8); +} + +static uint8_t ec_get_smi_event(void) +{ + ec_kbc_write_cmd(0x56); + return ec_kbc_read_ob(); +} + +static void ec_process_smi(uint8_t src) +{ + /* + * Reading the SMI source satisfies the EC in terms of responding to + * the event, regardless of whether we take an action or not. + */ + + printk(BIOS_DEBUG, "Unhandled EC_SMI event 0x%x\n", src); +} + +static void handle_ec_smi(void) +{ + uint8_t src; + + while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) + ec_process_smi(src); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SMI)) + handle_ec_smi(); +} + +int mainboard_smi_apmc(u8 data) +{ + printk(BIOS_INFO, "mainboard_smi_apmc(%02x)\n", data); + + switch (data) { + case APM_CNT_ACPI_ENABLE: + printk(BIOS_DEBUG, "Enable ACPI mode\n"); + ec_enter_acpi_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET1, GPI_IS_SCI); + gpi_route_interrupt(GPE_PALMDET2, GPI_IS_SCI); + break; + case APM_CNT_ACPI_DISABLE: + printk(BIOS_DEBUG, "Disable ACPI mode\n"); + ec_enter_apm_mode(); + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + break; + default: + printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data); + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == S3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } +} |