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authorNicolas Reinecke <nr@das-labor.org>2015-10-01 15:34:37 +0200
committerMartin Roth <martinroth@google.com>2016-04-13 17:54:46 +0200
commit2bffa8aa8418a7029615b492c80508733bba1231 (patch)
treecf3dc5e64b04d684e343617431267355fbe72d5e /src/mainboard/lenovo/t420/devicetree.cb
parent888a98b872ed88f70b76103a95ef5d4140cfe2d7 (diff)
downloadcoreboot-2bffa8aa8418a7029615b492c80508733bba1231.tar.xz
lenovo/t420: Add new port
This is based on t420s. Tested on a T420 without discrete GPU. There is no support for nvidia gpu and optimus. Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: Iru Cai <mytbk920423@gmail.com> Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8 Reviewed-on: https://review.coreboot.org/11765 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/lenovo/t420/devicetree.cb')
-rw-r--r--src/mainboard/lenovo/t420/devicetree.cb180
1 files changed, 180 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
new file mode 100644
index 0000000000..8041e5b2e2
--- /dev/null
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -0,0 +1,180 @@
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "1"
+ register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
+ register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
+ register "gfx.use_spread_spectrum_clock" = "1"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gpu_cpu_backlight" = "0x1155"
+ register "gpu_pch_backlight" = "0x06100610"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA988B
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21ce
+ end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on
+ subsystemid 0x17aa 0x21ce
+ end # Integrated Graphics Controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) & 5 (eSATA)
+ register "sata_port_map" = "0x37"
+ # Set max SATA speed to 6.0 Gb/s
+ register "sata_interface_speed_support" = "0x3"
+
+ register "gen1_dec" = "0x7c1601"
+ register "gen2_dec" = "0x0c15e1"
+ register "gen4_dec" = "0x0c06a1"
+
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+ register "c2_latency" = "101" # c2 not supported
+ register "p_cnt_throttling_supported" = "1"
+
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on
+ subsystemid 0x17aa 0x21ce
+ end # Intel Gigabit Ethernet
+ device pci 1a.0 on
+ subsystemid 0x17aa 0x21ce
+ end # USB Enhanced Host Controller #2
+ device pci 1b.0 on
+ subsystemid 0x17aa 0x21ce
+ end # High Definition Audio Controller
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 on
+ subsystemid 0x17aa 0x21ce
+ end # PCIe Port #2 Integrated Wireless LAN
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on
+ subsystemid 0x17aa 0x21ce
+ end # PCIe Port #4 ExpressCard
+ device pci 1c.4 on
+ subsystemid 0x17aa 0x21ce
+ chip drivers/ricoh/rce822
+ register "sdwppol" = "1"
+ register "disable_mask" = "0x87"
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21ce
+ end
+ end
+ end # PCIe Port #5 (Ricoh SD & FW)
+ device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on
+ subsystemid 0x17aa 0x21ce
+ end # USB Enhanced Host Controller #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ subsystemid 0x17aa 0x21ce
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa7"
+ register "config1" = "0x01"
+ register "config2" = "0xa0"
+ register "config3" = "0xe2"
+
+ register "has_keyboard_backlight" = "0"
+
+ register "beepmask0" = "0x02"
+ register "beepmask1" = "0x86"
+ register "has_power_management_beeps" = "1"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xf0"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x00"
+ register "event7_enable" = "0xa1"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0x00"
+ register "eventb_enable" = "0x00"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x0d"
+ end
+ end # LPC Controller
+ device pci 1f.2 on
+ subsystemid 0x17aa 0x21ce
+ end # 6 port SATA AHCI Controller
+ device pci 1f.3 on
+ subsystemid 0x17aa 0x21ce
+ # eeprom, 8 virtual devices, same chip
+ chip drivers/i2c/at24rf08c
+ device i2c 54 on end
+ device i2c 55 on end
+ device i2c 56 on end
+ device i2c 57 on end
+ device i2c 5c on end
+ device i2c 5d on end
+ device i2c 5e on end
+ device i2c 5f on end
+ end
+ end # SMBus Controller
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on
+ subsystemid 0x17aa 0x21ce
+ end # Thermal
+ end
+ end
+end