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| author | Patrick Rudolph <siro@das-labor.org> | 2017-04-28 17:28:32 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-05-21 16:38:52 +0200 |
| commit | c670a41ca717aefced613aa304da0e95ae4f2a27 (patch) | |
| tree | 4249645aa69a049ac668a87050a64ac444bad3da /src/mainboard/lenovo/t420/devicetree.cb | |
| parent | ac27d3688a862074631e3a1390caf85c068d55cb (diff) | |
| download | coreboot-c670a41ca717aefced613aa304da0e95ae4f2a27.tar.xz | |
mb/lenvovo/*: Clean mainboard.c and devicetree
* Move board specific SPI registers to devicetree
* Remove unused headers
* Remove obsolete methods
* Fix coding style
* Fix Thinkpad L520 SPI lvscc register
Except for Thinkpad L520, no functional change has been done,
just moving stuff around.
Change-Id: I692a5632030fe2fedbe9a90f86251000f1360fb2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/t420/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/t420/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index a921f765cb..deb62b7166 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -75,6 +75,10 @@ chip northbridge/intel/sandybridge register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + # device specific SPI configuration + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R |