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authorArthur Heymans <arthur@aheymans.xyz>2019-06-16 23:29:23 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 09:00:57 +0000
commit6beaef983aee5d886f6f8571855a92d608d98a17 (patch)
tree9c7f858bc7baa36d9e18ed84ea61d742559922c2 /src/mainboard/lenovo/t420
parent4821a0e135ff2d60f552203d2724ae2d44850623 (diff)
downloadcoreboot-6beaef983aee5d886f6f8571855a92d608d98a17.tar.xz
sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/t420')
-rw-r--r--src/mainboard/lenovo/t420/romstage.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 806c72a3be..ebf5aed0f1 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -56,10 +56,6 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
- pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
-
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}