summaryrefslogtreecommitdiff
path: root/src/mainboard/lenovo/t420
diff options
context:
space:
mode:
authorNico Huber <nico.h@gmx.de>2018-01-14 12:34:43 +0100
committerMartin Roth <martinroth@google.com>2018-01-23 05:25:41 +0000
commitff4025c5f789b80e6552dd887c34c34642a98c64 (patch)
tree852784fb6548c414d41dbdc93f4de6b5b191f9a6 /src/mainboard/lenovo/t420
parent101485c73dbb7eb8d89fbfda1c1bf9a5e495b536 (diff)
downloadcoreboot-ff4025c5f789b80e6552dd887c34c34642a98c64.tar.xz
sb/intel/bd82x6x: Reduce function-disable mess
Most affected boards set the function disabled (FD) register to an arbitrary state dumped from systems running the vendor BIOS. This makes it impossible to enable the devices in devicetree and a pretty big mess of course because nobody cared to keep the register in sync with the devicetree. To get completely rid of most of the writes to FD, move setting of PCH_DISABLE_ALWAYS into the southbridge code where it belongs. Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/23255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/t420')
-rw-r--r--src/mainboard/lenovo/t420/romstage.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index 9f178ea741..36e83a3c72 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -60,12 +60,11 @@ void pch_enable_lpc(void)
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}
-void rcba_config(void)
+void mainboard_rcba_config(void)
{
- /* Disable unused devices (board specific) */
- RCBA32(FD) = 0x1ea51fe3;
RCBA32(BUC) = 0;
}
+
// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0: system port 4, OC0 */