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| author | Nicolas Reinecke <nr@das-labor.org> | 2015-02-01 02:53:35 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-10 23:53:17 +0100 |
| commit | b0922f0183cb50b9714285c539c387956d86814c (patch) | |
| tree | 95d390fda6c2e8e0c95afc983c52284e33417b12 /src/mainboard/lenovo/t420s/devicetree.cb | |
| parent | 60ef456f46d81faa4f15b8a49b39037037b8b643 (diff) | |
| download | coreboot-b0922f0183cb50b9714285c539c387956d86814c.tar.xz | |
lenovo: fix smi gpe + wakeup pin for t420s t520 t530 x220 x230
Set correct gpio routing and enable bits for EC SMI gpio and EC WAKE gpio.
Verified with schematics.
Change-Id: Ie3b98c4456a870c881e7663b19eb8ca8e5564c5c
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8358
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/lenovo/t420s/devicetree.cb')
| -rw-r--r-- | src/mainboard/lenovo/t420s/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 990b576c70..7fd6a53ce7 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -54,7 +54,7 @@ chip northbridge/intel/sandybridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "alt_gp_smi_en" = "0x0000" register "gpi1_routing" = "2" - register "gpi8_routing" = "2" + register "gpi13_routing" = "2" # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) register "sata_port_map" = "0x17" |