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| author | Nico Huber <nico.h@gmx.de> | 2019-11-17 00:58:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:49:41 +0000 |
| commit | 89b8c238306e18792433717053649b61b91f57e6 (patch) | |
| tree | 4f2ad84c38ae5e69e9b1f4d0fb69740e7673e06e /src/mainboard/lenovo/t420s | |
| parent | ce20697513b1a6455c743aef43d40f91b0085af9 (diff) | |
| download | coreboot-89b8c238306e18792433717053649b61b91f57e6.tar.xz | |
mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16
This bit is used to indicate xHCI routing across reboots. If anything,
coreboot should act on it, not set it during boot. ASL code would be
supposed to set it.
Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/lenovo/t420s')
| -rw-r--r-- | src/mainboard/lenovo/t420s/early_init.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index 1357a0ae52..e2cdebfe35 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -49,11 +49,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 1, -1 }, /* P0 empty */ { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ |