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authorPhilipp Deppenwiese <zaolin@das-labor.org>2017-01-02 17:58:09 +0100
committerPatrick Rudolph <siro@das-labor.org>2017-05-19 09:53:48 +0200
commit714baa119b2ded203e148b381a4a3d1a74a91a68 (patch)
treecbb3ea675ff88a76d498557d494eb2b40521ac63 /src/mainboard/lenovo/t430/romstage.c
parentaeae34ffa4821a34505d28d140f2f60d5bca7da1 (diff)
downloadcoreboot-714baa119b2ded203e148b381a4a3d1a74a91a68.tar.xz
mainboard/lenovo/t430: Add Thinkpad T430 support
Tested and working: * HDD LED * Booting GNU Linux 4.9 from HDD using SeaBios * Booting GNU Linux 4.9 from USB using SeaBios * Native GFX init * All Fn function keys * Speakers * PCIe Wifi * Camera * WWAN * Fan (Dynamic Thermal Managment) * Flashing using internal programmer * Dual memory DIMMs running at up to DDR3-1866 * AC events * Touchpad, trackball and keyboard * USB3 ports running at SuperSpeed * Ethernet * Headphone jack * Speaker mute * Microphone mute * Volume keys * Fingerprint sensor * Lid switch * Thinklight * TPM (disable SeaBios CONFIG_TCGBIOS) * CMOS options: ** power_on_after_fail ** reboot_counter ** boot_option ** gfx_uma_size ** usb_always_on Untested: * Booting Windows * Hybrid graphics * Docking station * VGA Broken: * Wifi LED is always on Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/t430/romstage.c')
-rw-r--r--src/mainboard/lenovo/t430/romstage.c70
1 files changed, 70 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
new file mode 100644
index 0000000000..eb2d29e8cf
--- /dev/null
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+
+void pch_enable_lpc(void)
+{
+ /* EC Decode Range Port60/64, Port62/66 */
+ /* Enable TPM, EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC,
+ (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1);
+}
+
+void rcba_config(void)
+{
+ /* Disable unused devices (board specific, reserved only).
+ * FIXME: Test if reserved bits are read only. */
+ RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
+}
+
+/* FIXME: used T530 values here */
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 2, 3 },
+ { 1, 1, -1 },
+ { 1, 1, 2 },
+ { 1, 0, -1 },
+ { 0, 0, -1 },
+ { 1, 2, -1 },
+ { 1, 0, -1 },
+ { 1, 1, 5 },
+ { 1, 0, -1 },
+ { 1, 0, -1 },
+ { 1, 3, -1 },
+ { 1, 1, -1 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x51, id_only);
+}