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author | Bill XIE <persmule@gmail.com> | 2018-11-29 20:37:35 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-07 11:20:53 +0000 |
commit | 012ef7735d6878ef63aa0315863636bfb88e6c1f (patch) | |
tree | ba849a3d2d6b4ced66bccf34e48e256678265876 /src/mainboard/lenovo/t430s/devicetree.cb | |
parent | d2226060aac315c4420dc57569d90af5b0bf32c0 (diff) | |
download | coreboot-012ef7735d6878ef63aa0315863636bfb88e6c1f.tar.xz |
mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
The code is based on autoport and that for T430s
Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
Linux payload (Heads), Seabios may also work.
Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram
Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
corresponding SPD datum (3 observed) from CBFS (the mechanism may be
similar to that on x1_carbon_gen1 and s230u, but I do not know how
to find gpio ports for that, and SPD data stored in vendor firmware.)
Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/t430s/devicetree.cb')
-rw-r--r-- | src/mainboard/lenovo/t430s/devicetree.cb | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index b14d60c5e5..56e7f63e11 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -65,8 +65,8 @@ chip northbridge/intel/sandybridge register "gen4_dec" = "0x0c06a1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - - register "xhci_switchable_ports" = "0xf" + # Wire port 4 (wwan usb) to ehci for it lacks superspeed components + register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" @@ -74,6 +74,7 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported register "p_cnt_throttling_supported" = "1" + register "docking_supported" = "1" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" @@ -154,10 +155,6 @@ chip northbridge/intel/sandybridge register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" end end # LPC Controller device pci 1f.2 on |