mainboard/lenovo/t430s: Add ThinkPad T431s as a variant

The code is based on autoport and that for T430s

Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
  Linux payload (Heads), Seabios may also work.

Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram

Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
  corresponding SPD datum (3 observed) from CBFS (the mechanism may be
  similar to that on x1_carbon_gen1 and s230u, but I do not know how
  to find gpio ports for that, and SPD data stored in vendor firmware.)

Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

1 files changed, 1 insertions, 47 deletions

diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index cf7b3e836f..ab2bb0a442 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -15,13 +15,8 @@
  * GNU General Public License for more details.
  */
 
-#include <option.h>
-#include <arch/byteorder.h>
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <ec/lenovo/pmh7/pmh7.h>
 
 void pch_enable_lpc(void)
 {
@@ -41,47 +36,6 @@ void mainboard_rcba_config(void)
 {
 }
 
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 0,  0 }, /* P0:, OC 0 */
-	{ 1, 1,  1 }, /* P1: (EHCI debug), OC 1 */
-	{ 1, 1,  3 }, /* P2:  OC 3 */
-	{ 1, 0, -1 }, /* P3: no OC */
-	{ 1, 2, -1 }, /* P4: no OC */
-	{ 1, 1, -1 }, /* P5: no OC */
-	{ 1, 1, -1 }, /* P6: no OC */
-	{ 0, 1, -1 }, /* P7: empty, no OC */
-	{ 1, 1, -1 }, /* P8: smart card reader, no OC */
-	{ 1, 0,  5 }, /* P9:  (EHCI debug), OC 5 */
-	{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
-	{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
-	{ 0, 0, -1 }, /* P12: wlan, no OC */
-	{ 1, 1, -1 }, /* P13: camera, no OC */
-};
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
-void mainboard_early_init(int s3resume) {
-	u8 enable_peg;
-	if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS)
-		enable_peg = 0;
-
-	bool power_en = pmh7_dgpu_power_state();
-
-	if (enable_peg != power_en)
-		pmh7_dgpu_power_enable(!power_en);
-
-	if (!enable_peg) {
-		// Hide disabled dGPU device
-		u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
-		reg32 &= ~DEVEN_PEG10;
-
-		pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
-	}
-}
-
 void mainboard_config_superio(void)
 {
 }