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| author | Evgeny Zinoviev <me@ch1p.com> | 2018-08-30 02:18:48 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-05 10:04:20 +0000 |
| commit | 384e9aed8c477922c960e2cbd429bd3a15b371de (patch) | |
| tree | fd46db5b106df1a26c6e6fd5e93d1e1569924733 /src/mainboard/lenovo/t430s/romstage.c | |
| parent | ce1af8b0bf8569ad2d0ebc7bc7b0babe1579c7f2 (diff) | |
| download | coreboot-384e9aed8c477922c960e2cbd429bd3a15b371de.tar.xz | |
mb/lenovo: Support dual graphics for xx20/xx30 ThinkPads
Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/lenovo/t430s/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/t430s/romstage.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 3f6d9f2836..633ba3f142 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -15,12 +15,14 @@ * GNU General Public License for more details. */ +#include <option.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/pmh7/pmh7.h> void pch_enable_lpc(void) { @@ -64,6 +66,22 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { } void mainboard_early_init(int s3resume) { + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_PEG10; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } } void mainboard_config_superio(void) |