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| author | Chris Morgan <macromorgan@hotmail.com> | 2020-02-05 12:38:48 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-09 19:24:30 +0000 |
| commit | f8a13d5a2292c08515e4970d3f9bf5a9d0bee7d1 (patch) | |
| tree | 162a00493826c21ff9b9a4050717254784698a59 /src/mainboard/lenovo/t440p/romstage.c | |
| parent | 75372e5a7541a897b7d41d062957d045a1021ff9 (diff) | |
| download | coreboot-f8a13d5a2292c08515e4970d3f9bf5a9d0bee7d1.tar.xz | |
mb/lenovo/t440p: Enable dGPU on Lenovo T440P
Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of
the T430S. By default, it is set to be disabled however it can be
enabled via the nvram option enable_dual_graphics. Removed hybrid graphics
options too as they are not valid for the T440p. Tested on a T440P with
Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine
with Windows 10 1909 (machine check exception bluescreen).
Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/lenovo/t440p/romstage.c')
| -rw-r--r-- | src/mainboard/lenovo/t440p/romstage.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index c8c630bfde..283a52b460 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -22,6 +22,9 @@ #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <option.h> +#include <ec/lenovo/pmh7/pmh7.h> +#include <device/pci_ops.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -100,4 +103,21 @@ void mainboard_romstage_entry(void) }; romstage_common(&romstage_params); + + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } } |