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author | Nicolas Reinecke <nr@das-labor.org> | 2014-10-17 12:08:05 +0200 |
---|---|---|
committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-17 18:44:01 +0200 |
commit | 30d0aa9cdb43f24275869456b3688d066f280e0e (patch) | |
tree | 0b66a554ec0b594c8d95f79811c6125a944952f4 /src/mainboard/lenovo/t520/Kconfig | |
parent | 39937cc2fd28bcc754c0595f1327467499af40ea (diff) | |
download | coreboot-30d0aa9cdb43f24275869456b3688d066f280e0e.tar.xz |
lenovo/t520: Use native raminit over MRC blob
Native raminit for sandy/ivybridge was introduced in:
7686a56 sandy/ivybridge: Native raminit.
An additional current level is needed.
Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/7098
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/lenovo/t520/Kconfig')
-rw-r--r-- | src/mainboard/lenovo/t520/Kconfig | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 105d5dac9c..c20126dbe8 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SYSTEM_TYPE_LAPTOP select CPU_INTEL_SOCKET_RPGA988B - select NORTHBRIDGE_INTEL_SANDYBRIDGE + select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 @@ -27,7 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config HAVE_MRC_CACHE bool - default n + default y config HAVE_IFD_BIN bool @@ -53,10 +53,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config IRQ_SLOT_COUNT int default 18 |