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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 16:42:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:46:26 +0000 |
| commit | 9c538348d8ccaef2c3dd6b898a1f44b00ea59690 (patch) | |
| tree | 79eac3af79546b14b110b059e31eb18d33de4ce0 /src/mainboard/lenovo/t520 | |
| parent | 934b8da442a04978c6320299c616d3e8f05cb731 (diff) | |
| download | coreboot-9c538348d8ccaef2c3dd6b898a1f44b00ea59690.tar.xz | |
nb/intel/sandybridge: Make the mainboard_rcba_config hook optional
This also changes the name to mainboard_late_rcba_config to better
reflect what it does.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/lenovo/t520')
| -rw-r--r-- | src/mainboard/lenovo/t520/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 75e331e6d4..52898faa45 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -56,10 +56,6 @@ void pch_enable_lpc(void) pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -void mainboard_rcba_config(void) -{ -} - const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ |